25.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
Enabling operation by setting bit 0 (CLME) of the clock monitor mode register to 1
<Stop condition>
• While oscillation stabilization time is being counted after software STOP mode is released
• When the main clock is stopped
• When the sampling clock is stopped (Ring-OSC)
• When the CPU operates using Ring-OSC
CPU operation
Main clock
Ring-OSC clock
Reset
Notes: 1. Ring-OSC can be stopped by setting the RSTOP bit of the RCM register to 1
(1)
Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is gener-
ated as shown in Figure 25-3.
Main clock
Ring-OSC
reset signal
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Table 25-2: Operation Status of Clock Monitor (When CLM.CLME Bit = 1,
During Ring-OSC Operation) (CKSEL Connected to Ring-OSC)
Operation
clock
Mode
HALT mode
IDLE mode
STOP mode
-
-
2. The clock monitor is stopped while Ring-OSC is stopped.
Figure 25-3: When Oscillation of Main Clock Is Stopped
Internal
User's Manual U16702EE3V2UD00
Chapter 25 Clock Monitor
Status of Ring-OSC
Status of Main Clock
Oscillates
Oscillates
Stops
Stops
Oscillates
Stops
Stops
Four Ring Oscillation clocks
Status of Clock Moni-
Clock
tor
Note 2
Operates
Note 1
Stops
Note 1
Stops
Stops
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