NEC UPD703116 User Manual page 363

f
CLK
MUXTB0
MUXTB1
MUXCNT
5 1
TB1 TB0
Note 1
TB0Ey bit
Note 1
TB1Ey bit
WRITE_ENABLE_S
RELOAD_PRIMARY
CVSEm0 register
CVPEm0 register
RELOAD1
INTCCm
Notes 1. TB1Ey, TB0Ey bits of CMSEx0 register
2. No interrupt is generated due to compare match with counter differing from TB1Ey, TB0Ey bit
settings.
3. INTCC2m is generated to match the cycle from rising edge to falling edge of MUXTB0.
Remarks 1. f : Base clock
CLK
2. MUXCNT: Count value to sub-channel m
MUXTB0, MUXTB1: Multiplex signal of TM20, TM21
RELOAD1: Compare match signal
RELOAD_PRIMARY: Timing of write operation from CVSEm0 register to CVPEm0 register
WRITE_ENABLE_S: Timing of CVSEm0 register write operation
TB0: Count value of TM20
TB1: Count value of TM21
3. m = 1 to 4, x = 12, 34
CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-77. Compare Operation: Buffer-Less Mode
(When CMSEx0 Register's CCSEy Bit = 1, LNKEy Bit = Arbitrary,
BFEEy Bit = 0)
6 2 7 3 7
TB1 TB0 TB1 TB0 TB0
2
2
Note 3
User's Manual U14492EJ5V0UD
9 8 10 9 11
TB1 TB0 TB1 TB0 TB1
9
9
Note 2
Note 3
6 8 7 9 8 10
TB1 TB0 TB1 TB0 TB1 TB0
8
8
Note 3 Note 3
363