NEC UPD703116 User Manual page 137

32-bit single-chip microcontrollers

Table of Contents

Bit position

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

This status bit indicates whether DMA transfer through DMA channel n has ended or not.

This bit is read-only. It is set to 1 when DMA transfer ends and cleared (to 0) when it is

0: DMA transfer had not ended.

1: DMA transfer had ended.

When this bit is set to 1 when DMA transfer ends (at terminal count output), the Enn bit is

not cleared to 0 and the DMA transfer enable state is retained. When the next DMA

transfer start trigger is an interrupt from the on-chip peripheral I/O (hardware DMA), the

DMA transfer request can be accepted even when the TCn bit is not read. When the next

DMA transfer start trigger is the setting of the STGn bit to 1 (software DMA), the DMA

transfer request can be accepted by reading and clearing the TCn bit to 0.

When this bit is cleared to 0 when DMA transfer ends (at terminal count output), the Enn

bit is cleared to 0 and the DMA transfer disable state is entered. At the next DMA transfer

request, the setting of the Enn bit to 1 and the reading of the TCn bit are required.

When this bit is set to 1 during DMA transfer or DMA transfer suspension, DMA transfer is

forcibly terminated (refer to 6.12.1 Restrictions related to DMA transfer forcible

termination).

If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA

transfer is started.

Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This

bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA transfer is

forcibly suspended or terminated by means of setting the INITn bit to 1 or by NMI input.

0: DMA transfer disabled

1: DMA transfer enabled

After the Enn bit is set (1), do not set the Enn bit again until the number

of DMA transfers set by the DBCn register are complete or DMA transfer

is forcibly terminated using the INITn bit.

User's Manual U14492EJ5V0UD

Initial value