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(b) Error counter
The error counter value is incremented each time an error occurs and is decremented when a transmit or
receive operation ends normally. The count-up/count-down timing occurs at the first bit of the error
delimiter.
Receiving node has detected an error (except for bit errors
that occur in an active error flag or overload flag)
"Dominant (D)" is detected following error frame's error flag
output by the receiving node
Transmitting node has sent an error flag
[When error counter = ±0]
<1> When an ACK error was detected during error passive
status and a "dominant (D)" was not detected during
passive error flag output
<2> When a stuff error occurs in the arbitration field
Detection of bit error during output of active error flag or
overload flag (transmitting node with error active status)
Detection of bit error during output of active error flag or
overload flag (receiving node with error active status)
14 consecutive "dominant (D)" bits were detected from the
start of each node's active error flag or overload flag,
followed by detection of eight consecutive dominant bits.
Each node has detected eight consecutive dominant bits
after a passive error flag.
The transmitting node has completed a transmit operation
without any errors (±0 if error counter value is 0).
The receiving node has completed a receive operation
without any errors.
(c) Occurrence of bit error during intermission
In this case, an overload frame occurs.
Caution When an error occurs, error control is performed according to the contents of the
transmitting and receiving error counters as they existed prior to the error's occurrence.
The error counter value is incremented only after an error flag has been output.
538
CHAPTER 11 FCAN CONTROLLER
Table 11-16. Error Counter
Status
User's Manual U14492EJ5V0UD
Transmit Error
Receive Error Counter
Counter
(REC7 to REC0)
(TEC7 to TEC0)
No change
+1
No change
+8
+8
No change
+8
No change
No change
+8
+8
+8
–1
No change
• −1
No change
(1 ≤ REC7 to REC0 ≤ 127)
• ±0
(REC7 to REC0 = 0)
• 127 is set
(REC7 to REC0 > 127)
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