Clock Generator Operation; Clock Oscillator; Divider - NEC uPD784038 Series User Manual

4.3 CLOCK GENERATOR OPERATION

4.3.1 Clock Oscillator

(1) When using crystal/ceramic oscillation
The clock oscillation circuit starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode
is set by the standby control register (STBC). Oscillation is resumed when the STOP mode is released.
(2) When using external clock
The clock oscillation circuits supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.
The oscillation circuit operates as follows when the EXTC bit of the oscillation stabilization time specification register (OSTS)
is set to 1.
• The clock oscillation circuit is set in the external clock input mode.
• The clock oscillation circuit supplies the clock input to the X2 pin to the internal circuitry.
• The necessary circuit stops operating during the crystal/ceramic oscillation of the clock oscillation circuit, to reduce the
power dissipation.
• The STOP mode can be used even when the external clock is input.
• The oscillation stabilization time is shortened when the system is released from the STOP mode.
Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit of the Oscillation stabilization time specification
register (OSTS) must be cleared (to 0). If the EXTC bit is set (to 1), oscillation will stop.
2. If the STOP mode is used with external clock input, the EXTC bit of the OSTS must be set (to 1) before
setting the STOP mode. If the STOP mode is used when the EXTC bit is in the cleared (to 0) state, not
only will the clock generator consumption current not be reduced, but the µ µ µ µ µ PD784038 may also be
damaged or suffer reduced reliability.
3. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock
input to the X1 pin, to the X2 pin.
4.3.2

Divider

The divider performs 1/2, 1/4, 1/8, or 1/16 scaling of the clock oscillator output, and supplies the resulting clock to the CPU,
watchdog timer, noise elimination circuit, clocked serial interface (CSI), A/D converter, PWM, interrupt control circuit, and local
bus interface. The division ratio is specified by the CK0 and CK1 bits of the standby control register (STBC).
Controlling the division ratio to match the speed required by the CPU enables the overall power consumption to be reduced.
Also, the operating speed can be selected to match the supply voltage.
When RESET is input, the lowest speed (1/16) is selected.
If the division ratio of the divider circuit is changed, the maximum time shown in Table 4-1 is required to change the division
ratio, depending on the clock selected before change.
Instruction execution continues even while the division ratio is changed, and the clock is supplied with the previous division
ratio until the division ratio has been completely changed.
108
CHAPTER 4 CLOCK GENERATOR
Table 4-1 Time Required to Change Division Ratio
Previous Division Ratio Maximum Time Required for Change
1/2
1/4
1/8
1/16
User's Manual U11316EJ4V1UD
22/f
XX
24/f
XX
16/f
XX
16/f
XX