NEC UPD703116 User Manual page 453

(5) 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2
(TXSL1, TXSL2)
The TXSn register is a 9-bit/2-frame continuous transmission processing shift register (n = 1, 2).
Transmission is started by writing data to this register.
A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of
transmission of 1 frame or 2 frames including the TXSn data.
For 16-bit access to this register, specify TXSn, and for access to the lower 8 bits, specify TXSLn.
The TXSn register is write-only, in 16-bit units, and the TXSLn register is write-only, in 8-bit units.
Caution TXSn, TXSLn can be read, but since shifting is done in synchronization with the shift clock,
the data that is read cannot be guaranteed.
[2-frame continuous transmission shift register 1]
15 14 13 12
TXS1 TXS15 TXS14 TXS13 TXS12
[Transmit shift register L1]
[2-frame continuous transmission shift register 2]
15 14 13 12
TXS2 TXS15 TXS14 TXS13 TXS12
[Transmit shift register L2]
Bit position Bit name
15 to 0 TXB15 to
TXB0
CHAPTER 10 SERIAL INTERFACE FUNCTION
11 10 9 8 7 6
TXS11 TXS10 TXS9 TXS8 TXS7 TXS6
7 6
TXSL1 TXS7 TXS6
11 10 9 8 7 6
TXS11 TXS10 TXS9 TXS8 TXS7 TXS6
7 6
TXSL2 TXS7 TXS6
Writes transmit data.
User's Manual U14492EJ5V0UD
5 4 3 2 1 0
TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
5 4 3 2 1 0
TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
5 4 3 2 1 0
TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
5 4 3 2 1 0
TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
Function
Address Initial value
FFFFFA24H Undefined
Address Initial value
FFFFFA26H Undefined
Address Initial value
FFFFFA44H Undefined
Address Initial value
FFFFFA46H Undefined
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