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(2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control)
[Setting procedure]
(a) Set PWM mode 0 (symmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also
set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1).
(b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register. The transfer operation
from BFCMn3 to CM0n3 is set with bit BFTE3, and the transfer operation from BFCMn0 to BFCMn2 to
CM0n0 to CM0n2 is set with bit BFTEN.
(c) Set the initial values.
(i) Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register.
(ii) Set the half-cycle width of the PWM cycle in BFCMn3.
• PWM cycle = BFCMn3 value × 2 × TM0n count clock
(The TM0n count clock is set with the TMC0n register.)
(iii) Set the dead-time width in DTRRn.
• Dead-time width = (DTRRn + 1)/f
f
: Base clock
CLK
(iv) Set the set/reset timing of the F/F used in the PWM cycle in BFCMn0 to BFCMn2.
(d) Clear (0) the TM0CEDn bit of the TMC0n register to enable dead-time timer operation. Set TM0CEDn = 1
when not using dead time.
(e) Setting (1) the TM0CEn bit of the TMC0n register starts TM0n counting, and a 6-channel PWM signal is
output from pins TO0n0 to TO0n5.
Cautions 1. Setting CM0n3 to 0000H is prohibited.
2. Setting BFCMnx > BFCMn3 is prohibited when the TM0CEn bit of the TMC0n register = 0
because output of the TO0n0 to TO0n5 pins is inverted from the setting (x = 0 to 2). In
addition, setting BFCMnx > BFCMn3 is also prohibited when the TM0CEn bit of the
TMC0n register = 1 and the CM0nx register = 0.
Remark
The TM0CEn bit of the TMC0n register indicates transfer operation under the following conditions.
• When TM0CEn bit of TMC0n register is 0
Transfer to the CM0n0 to CM0n2 registers is performed at the next base clock (f
to registers BFCMn0 to BFCMn2.
• When TM0CEn bit of TMC0n register is 1
The value of the BFCMn0 to BFCMn2 registers is transferred to the CM0n0 to CM0n2 registers
upon occurrence of the INTTM0n interrupt. Transfer enable/disable at this time is controlled by
bit BFTEN of the TMC0n register.
CHAPTER 9 TIMER/COUNTER FUNCTION
CLK
User's Manual U14492EJ5V0UD
) after writing
CLK
251
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