NEC UPD703116 User Manual page 394

(2) PWM output
By setting the TMC30 and TMC31 registers as shown in Figure 9-98, timer 3 can output a PWM of the
frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register with the values that were
set in advance in the CC30 and CC31 registers as the intervals.
When the counter value of the TM3 register matches the setting value of the CC30 register, the TO3 output
becomes active. Then, when the count value of the TM3 register matches the setting value of the CC31
register, the TO3 output becomes inactive. The TM3 register continues counting, and when an overflow
occurs, clears the count value to 0000H and continues counting. This enables a PWM of the frequency
determined by the setting of the CS2 to CS0 bits of the TMC30 register to be output. When the setting value
of the CC30 register and the setting value of the CC31 register are the same, the TO3 output remains
inactive and does not change.
The active level of TO3 output can be set by the ALV bit of the TMC31 register.
Figure 9-98. Contents of Register Settings When Timer 3 Is Used for PWM Output
TM3OVF CS2
0/1 0/1
TMC30
OST ENT1 ALV
TMC31 0 1
Remark 0/1: Set to 0 or 1 as necessary
394
CHAPTER 9 TIMER/COUNTER FUNCTION
CS1 CS0 TM3CETM3CAE
0/1 0/1 0 0
ETI CCLR ECLR CMS1 CMS0
0/1 0/1 0 0/1
User's Manual U14492EJ5V0UD
1 1
Supply input clocks to internal units
Enable count operation
1 1
Use CC30 register as compare register
Use CC31 register as compare register
Disable clearing of TM3 register due to
match with CC30 register
Enable external pulse output (TO3)
Continue counting after TM3 register
overflows