Operation - NEC UPD703116 User Manual

9.3.5 Operation

(1) Edge detection
The edge detection timing is shown below.
f
CLK
Note
TINEx, TCLR2,
TCOUNTEn
MUXTB0
CT
ED1, ED2
ECLR
Note Set values of TESnE1, TESnE0 bits and CESE1, CESE0 bits of CSE0 register, and IESEx1, IESEx0 bits
of SESE0 register.
Remarks 1. f : Base clock
CLK
2. CT: TM2n count signal input in the 16-bit mode
ECLR: External control signal input from TCLR2 input
ED1, ED2: Capture event signal input from edge selector
MUXTB0: TM20 multiplex signal
TCOUNTEn: Timer 2 count enable signal input
TINEx: Timer 2 sub-channel x capture event signal input
3. n = 0, 1
x = 0 to 5
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CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-66. Edge Detection Timing
00B 01B
User's Manual U14492EJ5V0UD
10B 11B