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8.4 PLL Lockup
The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP
mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called a
lockup state, and the stabilized state is called a lock state.
(1) Lock register (LOCKR)
The lock register (LOCKR) has a LOCK flag that reflects the stabilized state of the PLL frequency.
This register is read-only, in 8-bit or 1-bit units.
Caution When the PLL is locked, the LOCK flag is 0. If the system then enters an unlocked state
due to a standby, the LOCK flag becomes 1. If anything other than a standby causes the
system to enter an unlocked state, the LOCK flag is not affected (LOCK = 0).
7
6
LOCKR
0
0
Bit position
Bit name
0
LOCK
If the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control
processing that depends on software execution speed, such as real-time processing, be sure to judge the LOCK flag
using software immediately after operation begins so that processing does not begin until after the clock stabilizes.
On the other hand, static processing such as the setting of internal hardware or the initialization of register data or
memory data can be executed without waiting for the LOCK flag to be reset.
The relationship between the oscillation stabilization time (the time from when the resonator starts to oscillate until
the input waveform stabilizes) when a resonator is used, and the PLL lockup time (the time until frequency stabilizes)
is shown below.
Oscillation stabilization time < PLL lockup time
CHAPTER 8 CLOCK GENERATION FUNCTION
5
4
3
0
0
0
This is a read-only flag that indicates the PLL state. This flag holds the value 0 as
long as a lockup state is maintained and is not initialized by a system reset.
0: Indicates that the PLL is locked.
1: Indicates that the PLL is not locked (UNLOCK state).
User's Manual U14492EJ5V0UD
2
1
<0>
0
0
LOCK
FFFFF824H 0000000xB
Function
Address
Initial value
203
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