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Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/5)
CLKOUT (Output)
A16 to A23 (Output)
AD8 to AD15 (I/O)
AD0 to AD7 (I/O)
ASTB (Output)
RD (Output)
UWR, LWR (Output)
CSn (Output)
WAIT (Input)
Note AD0 to AD7 output invalid data when accessed to odd-numbered address byte data.
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
3. n = 0 to 7
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
(d) On a write (0 wait insertion, for 8-bit data bus)
T1
Address
H
User's Manual U14492EJ5V0UD
T2
T3
Address
Address
Note
Data
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