Clock Control Register (Ckc) - NEC UPD703116 User Manual

8.3.4 Clock control register (CKC)

The clock control register is an 8-bit register that controls the internal system clock (f
written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous
program execution.
This register can be read/written in 8-bit units.
Caution Do not change bits CKDIV2 to CKDIV0 in direct mode.
7 6
CKC 0 0
Bit position Bit name
5 TBCS
4 CESEL
2 to 0 CKDIV2 to
CKDIV0
Example Clock generator settings
Operation CKSEL Pin
Mode
Direct mode High-level input
PLL mode Low-level input
Other than above
200
CHAPTER 8 CLOCK GENERATION FUNCTION
5 4 3
TBCS CESEL 0
Selects the time base counter clock.
8
0: f /2
X
9
1: f /2
X
For details, see 8.6.2 Time base counter (TBC).
Specifies the functions of the X1 and X2 pins.
0: A resonator is connected to the X1 and X2 pins
1: An external clock is connected to the X1 pin
When CESEL = 1, the oscillator feedback loop is disconnected to prevent current
leak in software STOP mode.
Sets the internal system clock frequency (f
CKDIV2 CKDIV1 CKDIV0
0 0
0 0
0 1
1 1
Other than above
Caution When changing the internal system clock during operation,
be sure to set the clock to be changed after setting the
CKDIV2 to CKDIV0 bits to 000 (f
CKC Register
CKDIV2 CKDIV1
0 0
0 0
0 0
0 1
1 1
User's Manual U14492EJ5V0UD
2 1 0
CKDIV2 CKDIV1 CKDIV0 FFFFF822H
Function
) when PLL mode is used.
XX
Internal system clock (f
0 f
X
1 2.5 × f
X
1 5 × f
X
1 10 × f
X
Setting prohibited
).
X
Input Clock (f
CKDIV0
0 16 MHz
0 5 MHz
1 5 MHz
1 5 MHz
1 5 MHz
Setting prohibited
) in PLL mode. It can be
XX
Address Initial value
00H
)
XX
) Internal System
X
Clock (f )
XX
8 MHz
5 MHz
12.5 MHz
25 MHz
50 MHz
Setting prohibited