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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/5)
(b) On a read (0 wait, address setup wait, address hold wait state insertion)
TASW
T1
TAHW
T2
T3
CLKOUT (Output)
Address
A16 to A23 (Output)
AD0 to AD15 (I/O)
Address
Data
ASTB (Output)
RD (Output)
H
UWR, LWR (Output)
CSn (Output)
WAIT (Input)
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
3. n = 0 to 7
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User's Manual U14492EJ5V0UD
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