NEC UPD703116 User Manual page 475

32-bit single-chip microcontrollers
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(3) Allowable baud rate range during reception
The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception
is shown below.
Caution The equations described below should be used to set the baud rate error during reception
so that it always is within the allowable error range.
Figure 10-24. Allowable Baud Rate Range During Reception
UARTn
transfer rate
Minimum allowable
transfer rate
Maximum allowable
transfer rate
As shown in Figure 10-24, after the start bit is detected, the receive data latch timing is determined according
to the counter that was set by the PRSCMn register. If all data up to the final data (stop bit) is in time for this
latch timing, the data can be received normally.
If this is applied to 11-bit reception, the following is theoretically true.
–1
FL = (Brate)
Brate: UARTn baud rate
k:
PRSCMn register setting value
FL:
1-bit data length
When the latch timing margin is 2 clocks of f
follows (f
: Internal system clock).
XX
=
×
FL
min
11
FL
CHAPTER 10 SERIAL INTERFACE FUNCTION
Latch timing
Start bit
Bit 0
Bit 1
FL
Start bit
Bit 0
Bit 1
Start bit
Bit 0
Bit 1
+
k
2
21
k
2
×
=
FL
2
k
2
k
User's Manual U14492EJ5V0UD
Bit 7
Parity bit
1 data frame (11 × FL)
Bit 7
Parity bit
FLmin
Bit 7
FLmax
/2, the minimum allowable transfer rate (FLmin) is as
XX
FL
Stop bit
Stop bit
Parity bit
Stop bit
475

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