NEC UPD703116 User Manual page 461

(c) Reception completion interrupt request
When reception of one frame of data has been completed (stop bit detection) when the RXEn bit of the
ASIMn0 register = 1, the receive data in the shift register is transferred to RXBn/RXBLn and a reception
completion interrupt request (INTSRn) is generated after 1 frame or 2 frames of data have been
transferred to RXBn/RXBLn.
A reception completion interrupt is also generated upon detection of an error.
When the RXEn bit = 0 (reception disabled), no reception completion interrupt is generated.
Figure 10-19. Asynchronous Serial Interface Reception Completion Interrupt Timing
8 serial clocks
RXDn (input)
INTSRn interrupt
Flag in reception
(SIRn)
8 serial clocks
RXDn (input)
INTSRn interrupt
Flag in reception
(SIRn)
8 serial clocks
RXDn (input)
INTSRn interrupt
Flag in reception
(SIRn)
CHAPTER 10 SERIAL INTERFACE FUNCTION
(a) When stop bit length = 1 bit
D0 D1 D2
Start
(b) When stop bit length = 2 bits
Start
D0 D1 D2
(c) In 2-frame continuous transmission mode
Parity Stop
D0 D1
Start
1st frame
User's Manual U14492EJ5V0UD
D6 D7 Parity
Parity
D6 D7
Start
D1 D5 D6 D7
2nd frame
8 serial clocks
Stop
8 serial clocks
Stop
8 serial clocks
Parity Stop
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