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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5)
These registers specify the valid edge for external interrupt requests input to timer 2 (INTP20 to INTP25).
The correspondence between each register and the external interrupt request that register controls is shown
below.
• FEM0: INTP20
• FEM1: INTP21
• FEM2: INTP22
• FEM3: INTP23
• FEM4: INTP24
• FEM5: INTP25
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling
edges).
These registers can be read/written in 8-bit or 1-bit units.
Cautions 1. The STFTE bit of timer 2 clock stop register 0 (STOPTE0) must be cleared (0) before
using the TI2/INTP20, TO21/INTP21, TO22/INTP22, TO23/INTP23, TO24/INTP24, and
TCLR2/INTP25 pins as INTP20, INTP21, INTP22, INTP23, INTP24, and INTP25, even if not
using timer 2.
2. Before setting the INTP2n pin to the trigger mode, set the PMC2 register. If the PMC2
register is set after the FEMn register has been set, an illegal interrupt may occur as
soon as the PMC2 register is set (n = 0 to 5).
3. The noise elimination function starts operating by setting the CEEn bit of the TCRE0
register to 1 (enabling count operations).
User's Manual U14492EJ5V0UD
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