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15
<14>
<13>
12
TCRE0
CASE1
CLRE1
CEE1
ECRE1
Bit position
Bit name
15
CASE1
14, 6
CLREn
13, 5
CEEn
12, 4
ECREn
Remark
n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
11
10
9
8
7
<6>
ECEE1
OSTE1
UDSE11
UDSE10
0
CLRE0
Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of
TM20 (carry count)).
0: Not connected in cascade
1: 32-bit cascade operation mode
Notes 1. TM21 counts at CT signal input in the count enabled state.
2. TM21 counts at CTC and CASC signal inputs in the count enabled state.
3. Only the capture register mode can be used for the capture/compare
register.
Cautions 1. When CASE1 = 1, set the TByE1 and TByE0 bits of the CMSEx0
register to 11 (x = 12, 34, y: When x = 12, y = 1, 2, and when x =
34, y = 3, 4).
2. When CASE1 = 0, TCOUNTE1 is selected as the count of TM21.
When CASE1 = 1, TCOUNTE0 and the TM20 overflow signal are
selected as the count of TM21.
Specifies software clear for TM2n.
0: TM2n operation continued
1: TM2n count value cleared (0)
Caution
Do not perform the software clear and hardware clear operations
simultaneously.
Specifies TM2n count operation enable/disable.
0: Count operation stopped
1: Count operation enabled
Specifies TM2n external clear (TCLR2) operation enable/disable via ECLR signal
input.
0: TM2n external clear (TCLR2) operation not enabled
1: TM2n external clear (TCLR2) operation enabled
Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n
external clear operation is not performed.
2. When the count value is cleared by inputting the ECLR signal
while ECREn = 1, the ECREn = 1 setting must be held for at least
one of the internal count clocks set by the CSEn2 to CSEn0 bits
of the CSE0 register.
3. In the 32-bit cascade operation mode (CASE1 = 1), only TM21 is
affected by the ECREn bit setting.
User's Manual U14492EJ5V0UD
<5>
4
3
2
1
0
CEE0
ECRE0
ECEE0
OSTE0
UDSE01
UDSE00
Function
Note 1
Notes 2, 3
(1/2)
Address
Initial value
FFFFF646H
0000H
339
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