NEC UPD703116 User Manual page 302

Bit position Bit name
1, 0 CLR1, CLR0
Remark n = 0, 1
302
CHAPTER 9 TIMER/COUNTER FUNCTION
Controls TM1n clear operation in UDC mode A.
CLR1 CLR0
0 0 Clear only by external input (TCLR1n)
0 1 Clear upon match of TM1n count value and CM1n0 set
value
1 0 Clear by TCLR1n input or upon match of TM1n count
value and CM1n0 set value
1 1 Don't clear
Cautions 1. Clearing by match of the TM1n count value and CM1n0 set value
is valid only during TM1n up-count operation (TM1n is not
cleared during TM1n down-count operation).
2. The CLR1 and CLR0 bit settings are invalid in general-purpose
timer mode (CMD bit of TUMn register = 0).
3. The CLR1 and CLR0 bit settings are invalid in UDC mode B
(MSEL bit of TUMn register = 1).
4. When clearing by TCLR1n has been enabled with bits CLR1 and
CLR0, clearing is performed whether the value of the TM1CEn bit
is 1 or 0.
User's Manual U14492EJ5V0UD
Function
Specify TM1n clear source
(2/2)