Dma Transfer Start Factors - NEC UPD703116 User Manual

6.9 DMA Transfer Start Factors

There are two types of DMA transfer start factors, as shown below.
Cautions 1. Do not use two or more start factors ((1) and (2)) in combination for the same channel (if two
or more start factors are generated at the same time, only one of them is valid, but the valid
start factor cannot be identified). The operation is not guaranteed if two or more start factors
are used in combination.
2. If DMA transfer is started via software and if the software does not correctly detect whether
the expected DMA transfer operation has been completed through manipulation (setting to 1)
of the STGn bit of the DCHCn register, it cannot be guaranteed whether the next (second)
manipulation of the STGn bit corresponds to the start of "the next DMA transfer expected by
software" (n = 0 to 3).
For example, suppose single transfer is started by manipulating the STGn bit. Even if the
STGn bit is manipulated next (the second time) without checking by software whether the
single transfer has actually been executed, the next (second) DMA transfer is not always
executed. This is because the STGn bit may be manipulated the second time before the first
DMA transfer is started or completed because, for example, DMA transfer with a higher
priority had already been started when the STGn bit was manipulated for the first time. It is
therefore necessary to manipulate the STGn bit next time (the second time) after checking
whether DMA transfer started by the first manipulation of the STGn bit has been completed.
Completion of DMA transfer can be checked by checking the contents of the DBCn register.
(1) Request from software
If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3).
• STGn bit = 1
• Enn bit = 1
• TCn bit = 0
(2) Request from on-chip peripheral I/O
If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued
from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3).
• Enn bit = 1
• TCn bit = 0
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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