NEC UPD703116 User Manual page 321

(c) Operation in UDC mode A
(i) Interval operation
The operations at the count clock following match of the TM1n count value and the CM1n0 set value
are as follows.
• In case of up-count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated.
• In case of down-count operation: The TM1n count value is decremented (−1) and the INTCM1n0
interrupt is generated.
Remark The interval operation can be combined with the transfer operation.
(ii) Transfer operation
If TM1n becomes 0000H during down counting when the RLEN bit of the TMC1n register is 1, the
CM1n0 register set value is transferred to TM1n at the next count clock.
Remarks 1. Transfer enable/disable can be set with the RLEN bit of the TMC1n register.
2. The transfer operation can be combined with the interval operation.
Figure 9-57. Example of TM1n Operation When Interval Operation and Transfer Operation Are Combined
Remark n = 0, 1
(iii) Compare function
TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TM1n count value and the set value of one of the compare registers match, a match
interrupt (INTCM1n0, INTCM1n1, INTCC1n0
Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register
mode.
(iv) Capture function
TM1n connects two capture/compare register (CC1n0, CC1n1) channels.
When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in
synchronization with the corresponding capture trigger signal.
INTCC1n1) is generated upon detection of the valid edge.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM1n0 set value
TM1n count value
0000H
TM1n and CM1n0 match
& timer clear
Up count
User's Manual U14492EJ5V0UD
TM1n underflow
& CM1n0 data transfer
Down count
Note Note
, INTCC1n1 ) is output.
A capture interrupt (INTCC1n0,
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