NEC UPD703116 User Manual page 784

(10) UART1, UART2 timing (2/2)
(b) Clocked slave mode
µ
= –40 to +85°C:
(T PD703116, 703116(A), 70F3116, 70F3116(A),
A
= –40 to +110°C: µ
T PD703116(A1), 70F3116(A1),
A
V = CV = 3.0 to 3.6 V, V
DD3 DD
output pin load capacitance: C
Parameter
ASCKn cycle
ASCKn high-level width
ASCKn low-level width
RXDn setup time (to ASCKn↑)
RXDn hold time (from ASCKn↑)
TXDn output delay time (from ASCKn↓)
TXDn output hold time (from ASCKn↑)
Remarks 1. T = 2t
CYK
2. k: Setting value of PRSCMn register of UARTn
3. n = 1, 2
ASCKn (I/O)
RXDn (input)
TXDn (output)
Remark n = 1, 2
784
CHAPTER 18 ELECTRICAL SPECIFICATIONS
= 5 V ±0.5 V, V
= V
DD5 SS3
= 50 pF)
L
Symbol
<73> t
CYSK0
<74> t
WSK0H
<75> t
WSK0L
<76> t
SRXSK
<77> t
HSKRX
<78> t
DSKTX
<79> t
HSKTX
<73>
<75> <74>
<77>
<76>
Input data
<78>
Output data
User's Manual U14492EJ5V0UD
= CV = 0 V,
SS5 SS
Conditions MIN.
Input 1000
Input 4 T + 80
Input 4 T + 80
T + 10
T + 10
k T + 1.5 T
<79>
MAX. Unit
ns
ns
ns
ns
ns
2.5 T + 45 ns
ns