NEC UPD703116 User Manual page 211

32-bit single-chip microcontrollers
Table of Contents

Advertisement

(2) Release of HALT mode
HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request
(INTPn), or RESET pin input (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111).
(a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request
HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt
request regardless of the priority. However, if the system is set to HALT mode during an interrupt
servicing routine, operation will differ as follows.
(i) If an interrupt request is generated with a lower priority than that of the interrupt request that is
currently being serviced, HALT mode is released, but the newly generated interrupt request is not
acknowledged. The new interrupt request is held pending.
(ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority
than that of the interrupt request that is currently being serviced, HALT mode is released and the
newly generated interrupt request is acknowledged.
Table 8-3. Operation After HALT Mode Is Released by Interrupt Request
Release Source
Non-maskable interrupt request
Maskable interrupt request
(b) Release by RESET pin input
This is the same as a normal reset operation.
CHAPTER 8 CLOCK GENERATION FUNCTION
Enable Interrupt (EI) Status
Branch to handler address
Branch to handler address or
execute next instruction
User's Manual U14492EJ5V0UD
Disable Interrupt (DI) Status
Execute next instruction
211

Advertisement

Table of Contents
loading

Table of Contents