NEC UPD703116 User Manual page 258

Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0)
count value
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Note F/F is reset upon INTTM0n occurrence.
Remarks 1. n = 0, 1
2. x = 0 to 2
3. t: Dead time = (DTRRn + 1)/f
4. The above figure shows an active high case.
258
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a a
TM0n
CM0nx CM0nx
match match
CM0nx match
a 0000H
BFCM0nx
a
CM0nx
INTTM0n
INTCM0n3
F/F
DTMnx
t t
t
(f
CLK CLK
User's Manual U14492EJ5V0UD
CM0n3 CM0n3
0000H b
0000H 0000H
INTTM0n INTTM0n
INTCM0n3 INTCM0n3
Note
: Base clock)
CM0n3
b b
CM0nx CM0nx
match match
CM0nx match
c
b
INTTM0n
INTCM0n3
t t
t