Times Related To Dma Transfer - NEC UPD703116 User Manual

32-bit single-chip microcontrollers

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(2) Repeat setting the INITn bit of the DCHCn register until forcible termination of DMA transfer is

completed normally

The procedure is shown below.

<1> Copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register.

<2> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1.

<3> Read the value of DMA transfer count register n (DBCn) of the channel to be forcibly terminated, and

compare that value with the value copied in step <1>. If the two values do not match, repeat steps <2>

Cautions 1. If the DBCn register is read in step <3>, and if DMA transfer is stopped due to

2. With this procedure, it may take some time for the channel in question to be

6.13 Times Related to DMA Transfer

The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below.

Table 6-3. Number of Minimum Execution Clocks in DMA Cycle

<1> Time to respond to DMA request

<2> Memory access

If an external interrupt (INTPn) is specified as a factor of starting DMA transfer, noise elimination time

is added (n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, or 31).

Two clocks are required for the DMA cycle.

The minimum execution clock in the DMA cycle in each transfer mode is as follows.

Single transfer:

DMA response time (<1>) + Transfer source memory access (<2>) + 1

destination memory access (<2>)

Block transfer:

DMA response time (<1>) + (Transfer source memory access (<2>) + 1

destination memory access (<2>)) × Number of transfers

Note One clock is always inserted between the read cycle and write cycle of DMA transfer.

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

trouble, the remaining number of transfers will be read. If DMA transfer has been

forcibly terminated correctly, the initial number of transfers will be read.

forcibly terminated in an application in which DMA transfer of a channel other than

that to be forcibly terminated is frequently executed.

Internal RAM access

On-chip peripheral I/O

User's Manual U14492EJ5V0UD

Number of Minimum Execution Clocks

4 clocks + number of waits set by VSWC register