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(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers.
The base clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSR0 register.
The 8-bit counter divisor value can be set according to the MDL7 to MDL0 bits of the BRGC0 register.
(a) Clock selection register 0 (CKSR0)
The CKSR0 register is an 8-bit register for selecting the base clock (f
bits. The clock selected by the TPS3 to TPS0 bits becomes f
This register can be read/written in 8-bit units.
Cautions 1. The maximum allowable frequency of the base clock (f
when the system clock's frequency is 50 MHz, bits TPS3 to TPS0 cannot be set to
0000B.
To use 50 MHz, set the TPS3 to TPS0 bits to a value other than 0000B, and set the
UARTCAE0 bit of the ASIM0 register to 1.
2. If the TPS3 to TPS0 bits are to be overwritten, the UARTCAE0 bit of the ASIM0
register should be set to 0 first.
7
6
CKSR0
0
0
Bit position
Bit name
3 to 0
TPS3 to
TPS0
CHAPTER 10 SERIAL INTERFACE FUNCTION
5
4
3
0
0
TPS3
Specifies the base clock (f
TPS3
TPS2
TPS1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
Arbitrary Arbitrary Setting prohibited
Remark f
: Internal system clock
XX
User's Manual U14492EJ5V0UD
) according to the TPS3 to TPS0
CLK
of the transmission/reception module.
CLK
2
1
0
TPS2
TPS1
TPS0
Function
).
CLK
TPS0
Base clock (f
0
0
f
XX
0
1
f
/2
XX
1
0
f
/4
XX
1
1
f
/8
XX
0
0
f
/16
XX
0
1
f
/32
XX
1
0
f
/64
XX
1
1
f
/128
XX
0
0
f
/256
XX
0
1
f
/512
XX
1
0
f
/1024
XX
1
1
f
/2048
XX
) is 25 MHz. Therefore,
CLK
Address
Initial value
FFFFFA06H
00H
)
CLK
435
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