NEC UPD703116 User Manual page 269

32-bit single-chip microcontrollers
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(d) When BFCMnx = 0000H is set in software processing started by INTTM0n
Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2)
TM0n
count value
0000H
BFCMnx
CM0nx
Interrupt request
DTMnx
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. t: Dead time = (DTRRn + 1)/f
4. The above figure shows an active high case.
Since TM0n = CM0nx = 0000H match is detected during up counting by TM0n, the F/F is just set and
does not get reset. Therefore, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a high level,
and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a low level.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
Figure 9-28 shows the change timing from the 100% duty state.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
CM0nx
match
a
0000H
a
0000H
INTCM0n3
F/F
t
(f
: Base clock)
CLK
CLK
User's Manual U14492EJ5V0UD
CM0n3
0000H
0000H
0000H
0000H
INTTM0n
INTCM0n3
0000H
0000H
INTTM0n
269

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