Control Registers; Dma Source Address Registers 0 To 3 (Dsa0 To Dsa3) - NEC UPD703116 User Manual

32-bit single-chip microcontrollers

Table of Contents

6.3 Control Registers

These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They

are divided into two 16-bit registers, DSAnH and DSAnL.

Since these registers are 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified

during DMA transfer (refer to 6.8 Next Address Setting Function). In this case, if a new DSAn register is set, the

value set will be transferred to the slave register and enabled only if DMA transfer ends normally, and the TCn bit of

DMA channel control register n (DCHCn) has been set to 1 or the INITn bit of the DCHCn register has been set to 1 (n

(1) DMA source address registers 0H to 3H (DSA0H to DSA3H)

These registers can be read/written in 16-bit units.

Be sure to set bits 12 to 14 to 0. If they are set to 1, the operation is not guaranteed.

Cautions 1. When setting an address of an on-chip peripheral I/O register for the source address, be

sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-

chip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified.

2. Do not set the DSAnH register when DMA transfer has been suspended.

Bit position

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

0 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16

Specifies the DMA source address.

0: External memory, on-chip peripheral I/O

1: Internal RAM

Sets the DMA source addresses (A27 to A16). During DMA transfer, it stores the next

DMA transfer source address.

User's Manual U14492EJ5V0UD

Initial value