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(4) Reception operation
An awaiting reception state is set by setting UARTCAE0 bit to 1 in the ASIM0 register and then setting RXE0
bit to 1 in the ASIM0 register. To start the receive operation, start sampling at the falling edge when the
falling of the RXD0 pin is detected. If the RXD0 pin is low level at a start bit sampling point, the start bit is
recognized. When the receive operation begins, serial data is stored sequentially in the receive shift register
according to the baud rate that was set. A reception completion interrupt (INTSR0) is generated each time
the reception of one frame of data is completed. Normally, the receive data is transferred from receive buffer
register 0 (RXB0) to memory by this interrupt servicing.
(a) Reception enabled state
The receive operation is set to reception enabled state by setting the RXE0 bit in the ASIM0 register to 1.
• RXE0 bit = 1: Reception enabled state
• RXE0 bit = 0: Reception disabled state
In reception disabled state, the reception hardware stands by in the initial state. At this time, the contents
of receive buffer register 0 (RXB0) are retained, and no reception completion interrupt or reception error
interrupt is generated.
(b) Start of reception operation
A reception operation is started by the detection of a start bit.
The RXD0 pin is sampled according to the serial clock from the baud rate generator 0 (BRG0).
(c) Reception completion interrupt
When RXE0 = 1 in the ASIM0 register and the reception of one frame of data is completed (the stop bit is
detected), a reception completion interrupt (INTSR0) is generated and the receive data in the receive
shift register is transferred to the RXB0 register at the same time.
Also, if an overrun error (OVE bit of ASIS0 register = 1) occurs, the receive data at that time is not
transferred to receive buffer register 0 (RXB0), and either an INTSR0 signal or a reception error interrupt
(INTSER0) is generated according to the ISRM bit setting in the ASIM0 register.
Even if a parity error (PE bit of ASIS0 register = 1) or framing error (FE bit of ASIS0 register = 1) occurs
during a receive operation, the receive operation continues until stop bit is received, and after reception is
completed, either an INTSR0 signal or an INTSER0 signal is generated according to the ISRM bit setting
in the ASIM0 register (the receive data in the receive shift register is transferred to the RXB0 register).
If the RXE0 bit is cleared (0) during a receive operation, the receive operation is immediately stopped.
The contents of receive buffer register 0 (RXB0) and of the asynchronous serial interface status register
(ASIS0) at this time do not change, and no INTSR0 or INTSER0 signal is generated.
No INTSR0 or INTSER0 signal is generated when RXE0 = 0 (reception is disabled).
CHAPTER 10 SERIAL INTERFACE FUNCTION
User's Manual U14492EJ5V0UD
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