NEC UPD703116 User Manual page 229

32-bit single-chip microcontrollers
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Bit position
Bit name
4
BFTE3
3
BFTEN
2
MBFTE
Remark
n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
Specifies transfer of data from BFCMn3 register to CM0n3 register.
0: Transfer disabled
1: Transfer enabled
The transfer timing from the BFCMn3 register to the CM0n3 register is as follows.
BFTE3
TM0n operation mode
0
All modes
1
PWM mode 0 (symmetric
triangular wave)
1
PWM mode 1 (asymmetric
triangular wave)
1
PWM mode 2 (sawtooth wave)
When the BFTE3 bit = 1, the value of the BFCMn3 register is transferred to the
CM0n3 register upon occurrence of an INTTM0n or INTCM0n3 interrupt.
Specifies transfer of data from BFCMn0 to BFCMn2 registers to CM0n0 to CM0n2
registers.
0: Transfer disabled
1: Transfer enabled
BFTEN
TM0n operation mode
0
All modes
1
PWM mode 0 (symmetric
triangular wave)
1
PWM mode 1 (asymmetric
triangular wave)
1
PWM mode 2 (sawtooth wave)
When the BFTEN bit = 1, the values of the BFCMn0 to BFCMn2 registers are
transferred to the CM0n0 to CM0n2 registers upon occurrence of an INTTM0n or
INTCM0n3 interrupt.
When culling of INTTM0n and INTCM0n3 interrupts is set with the CUL02 to CUL00
bits, specifies whether enable or disable the BFTE3 and BFTEN bit settings upon
occurrence of an interrupt for culling.
0: Disable the set values of BFTE3, BFTEN bits upon occurrence of a culling
interrupt
1: Enable the set values of BFTE3, BFTEN bits upon occurrence of a culling
interrupt
The various combinations are as follows.
MBFTE
Operation upon occurrence of interrupt for culling
BFCMn0 to BFCMn2 →
BFTEN
0
CM0n0 to CM0n2 transfer
disabled
BFCMn0 to BFCMn2 →
1
CM0n0 to CM0n2 transfer
disabled
BFCMn3 → CM0n3
BFTE3
0
transfer disabled
BFCMn3 → CM0n3
1
transfer disabled
.
User's Manual U14492EJ5V0UD
Function
BFCMn3 → CM0n3 transfer
Don't transfer
INTTM0n
INTTM0n
INTCM0n3
BFCMn0 to BFCMn2 → CM0n0 to
CM0n2 transfer timing
Don't transfer
INTTM0n
INTTM0n, INTCM0n3
INTCM0n3
0
BFCMn0 to BFCMn2 → CM0n0
to CM0n2 transfer disabled
BFCMn0 to BFCMn2 → CM0n0
to CM0n2 transfer enabled
BFCMn3 → CM0n3 transfer
disabled
BFCMn3 → CM0n3 transfer
enabled
(3/4)
timing
1
229

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