NEC UPD703116 User Manual page 430

32-bit single-chip microcontrollers
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Figure 10-7. Asynchronous Serial Interface Reception Completion Interrupt Timing
RXD0 (input)
INTSR0 (output)
RXB0 register
Cautions 1. Even if a reception error occurs, be sure to read receive buffer register 0 (RXB0). If the
RXB0 register is not read, an overrun error will occur at the next data reception, and the
reception error state will continue indefinitely.
2. Reception is always performed with the stop bit length set to 1.
A second stop bit is ignored.
(5) Reception error
The three types of error that can occur during a receive operation are a parity error, framing error, or overrun
error. The data reception result is that the various flags of the ASIS0 register are set (1), and a reception
error interrupt (INTSER0) or a reception completion interrupt (INTSR0) is generated at the same time. The
ISRM bit of the ASIM0 register specifies whether an INTSER0 or INTSR0 signal is generated.
The type of error that occurred during reception can be detected by reading the contents of the ASIS0
register during the INTSER0 or INTSR0 interrupt servicing.
The contents of the ASIS0 register are cleared (0) by reading the ASIS0 register.
Error Flag
PE
FE
OVE
430
CHAPTER 10 SERIAL INTERFACE FUNCTION
Start
D0
D1
Table 10-2. Reception Error Causes
Reception Error
Parity error
The parity specification during transmission did not match
the parity of the reception data
Framing error
No stop bit was detected
Overrun error
The reception of the next data was completed before data
was read from receive buffer register 0 (RXB0)
User's Manual U14492EJ5V0UD
D2
D6
D7
Cause
Parity Stop

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