NEC UPD703116 User Manual page 460

(4) Reception operation
The reception wait status is entered by setting the RXEn bit of the ASIMn0 register to 1 (n = 1, 2). To start
the reception operation, first perform start bit detection. Start bit detection is done by performing sampling of
the RXDn pin. When the reception operation is started, serial data is stored to the receive shift register in
sequence at the set baud rate. Each time reception of 2 frames or 1 frame of RXBn or RXBLn data has been
completed, a reception completion interrupt (INTSRn) is generated. Receive data is transmitted from the
receive buffer (RXBn/RXBLn) to memory when this interrupt is serviced.
(a) Reception enabled status
The reception operation is enabled by setting (1) the RXEn bit of the ASIMn0 register.
• RXEn = 1: Reception enabled status
• RXEn = 0: Reception disabled status
In the reception disabled status, the reception hardware is in standby in an initialized state. At this time,
no reception completion interrupt is generated, and the contents of the receive buffer are held.
(b) Start of reception operation
The reception operation is started through detection of the start bit.
• In asynchronous mode (MOD bit of ASIMn1 register = 0)
The RXDn pin is sampled using the serial clock from the baud rate generator. After 8 serial clocks
have been output following detection of the falling edge of the RXDn pin, the RXDn pin is again
sampled. If a low level is detected at this time, the falling edge of the RXDn pin is interpreted as a
start bit, the operation shifts to reception processing, and the RXDn pin input is sampled from this
point on in units of 16 serial clock output.
If the high level is detected during sampling after 8 serial clocks from detection of the falling edge of
the RXDn pin, this falling edge is not recognized as a start bit. The serial clock counter that generates
the sample timing is initialized and stops, and input of the next falling edge is waited for.
• In synchronous mode (MOD bit of ASIMn1 register = 1)
The RXDn pin is sampled using the serial clock from the baud rate generator or at the rising edge of
serial clock I/O. If the RXDn pin is low level at this time, this is interpreted as a start bit and reception
processing starts.
If reception data is interrupted at the fixed low level during reception, reception of this receive data
(including error detection) is completed and reception completion interrupt is generated. However, even
if the RXD line is fixed at low level, the next reception operation is not started (start bit detection is not
performed).
Be sure to set the high level when restarting the reception operation. If the high level is not set, the start
bit detection position becomes undefined, and correct reception operation cannot be performed.
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CHAPTER 10 SERIAL INTERFACE FUNCTION
User's Manual U14492EJ5V0UD