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(ii) In case of contention between interrupt request and register access
Since continuous transfer has stopped once, executed as a new repeat transfer.
In the slave mode, a bit phase error transfer error results (refer to Figure 10-33).
In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal
data is sent.
Figure 10-33. Interrupt Request and Register Access Contention
SCKn
(I/O)
INTCSIn
interrupt
rq_clr
Reg_R/W
Remarks 1. n = 0, 1
2. rq_clr: Internal signal. Transfer request clear signal.
Reg_R/W:
CHAPTER 10 SERIAL INTERFACE FUNCTION
Transfer reservation period
Internal signal.
This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed.
User's Manual U14492EJ5V0UD
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