NEC UPD703116 User Manual page 325

(3) Interrupt signal output upon compare match
An interrupt signal is output when the count value of TM1n matches the set value of the CM1n0, CM1n1,
Note Note
CC1n0 , or CC1n1
Note When CC1n0 and CC1n1 are set to the compare register mode.
(CM1n1 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to f
Internal match signal
Remarks 1. n = 0, 1
2. f : Base clock
CLK
An interrupt signal such as illustrated in Figure 9-62 is output at the next count clock following a match of the
TM1n count value and the set value of a corresponding compare register.
(4) TM1UBDn flag (bit 0 of STATUSn register) operation
In the UDC mode (CMD bit of TUMn register = 1), the TM1UBDn flag changes as follows during TM1n
up/down count operation at every internal operation clock.
Count clock
TM1UBDn
Remark n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
register. The interrupt generation timing is as follows.
Figure 9-62. Interrupt Output upon Compare Match
f
CLK
Count clock
TM1n 0007H 0008H
CM1n1
INTCM1n1
Figure 9-63. TM1UBDn Flag Operation
TM1n 0000H 0001H 0000H
User's Manual U14492EJ5V0UD
0009H 000AH 000BH
0009H
0001H 0000H 0001H
/2)
CLK
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