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NEC V850E/VANSTORM Preliminary User's Manual

32-/16-bit single-chip microcontroller with can and van interfaces

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Preliminary User's Manual

V850E/VANSTORM

32-/16-bit Single-Chip Microcontroller

with CAN and VAN Interfaces

Hardware

µPD76F0018

Document No. U14879EE1V0UM00

Date Published August 2001

 NEC Corporation 2001

Printed in Germany

TM

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Page 1 Preliminary User’s Manual V850E/VANSTORM 32-/16-bit Single-Chip Microcontroller with CAN and VAN Interfaces Hardware µPD76F0018 Document No. U14879EE1V0UM00 Date Published August 2001  NEC Corporation 2001 Printed in Germany...
Page 2 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 3 The information in this document is current as of 20.07.2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC’s data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country.
Page 4: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
Page 5 Preface Readers This manual is intended for users who want to understand the functions of the V850E/VANSTORM. Purpose This manual presents the hardware manual of V850E/VANSTORM. Organization This system specification describes the following sections: • Pin function • CPU function •...
Page 6 [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 7: Table Of Contents
Table of Contents Chapter 1 Introduction ..........21 General .
Page 8 Bus Priority Order ........... . 144 Boundary Operation Conditions .
Page 9 7.4.3 Clock select pin ..........210 Power Saving Functions .
Page 10 11.3.1 Features ............320 11.3.2 Configuration .
Page 11 Chapter 14 A/D Converter ..........489 14.1 Features .
Page 12 19.4 Communication System ..........565 19.5 Flash Programming Circuitry .
Page 13 List of Figures Figure 1-1: Pin Configuration of the VANStorm Microcontroller ........... 24 Figure 1-2: Block Diagram of the VANStorm Microcontroller ............26 Figure 2-1: Pin I/O Circuits ......................51 Figure 3-1: CPU Register Set ....................... 54 Figure 3-2: Program Counter (PC) ....................55 Figure 3-3: Interrupt Source Register (ECR) ................
Page 14 Figure 6-23: Exception Trap Processing ..................198 Figure 6-24: Restore Processing from Exception Trap ..............199 Figure 6-25: Debug Trap Processing .................... 200 Figure 6-26: Restore Processing from Debug Trap ..............201 Figure 6-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline) ......204 Figure 7-1: Block Diagram of the Clock Generator ..............
Page 15 Figure 8-40: Timer E Compare Operation: Timing of Compare Match and Write Operation to Register ................277 Figure 8-41: Timer E Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 ....278 Figure 8-42: Timer E Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 ....279 Figure 8-43: Timer E Signal Output Operation: During Software Control ........
Page 16 Figure 11-43: Prescaler Mode Registers 0, 1 (PRSM0, PRSM1) ........... 348 Figure 11-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) ........349 Figure 12-1: Functional Blocks of the FCAN Interface ..............352 Figure 12-2: Memory Area of the FCAN System ................353 Figure 12-3: Clock Structure of the FCAN System ...............
Page 17 Figure 13-11: FV Status bit ......................462 Figure 13-12: Exceeded retry with MR[3..0] = 3 ................463 Figure 13-13: Update of the Status Register .................. 466 Figure 13-14: Message buffer structure for transmission ............... 472 Figure 13-15: Message buffer structure for reception ..............473 Figure 13-16: Message Status updating ..................
Page 18 Figure 15-32: Port AH Mode Register (PMAH) ................542 Figure 15-33: Port AH Mode Control Register (PMCAH) ..............543 Figure 15-34: Port DL (PDL) ......................544 Figure 15-35: Port DL Mode Register (PMDL) ................544 Figure 15-36: Port DL Mode Control Register (PMCDL) ..............545 Figure 15-37: Port CS (PCS) ......................
Page 19 List of Tables Table 3-1: Program Registers ......................55 Table 3-2: System Register Numbers .................... 56 Table 3-3: Register Initial Values by Operation Modes ..............58 Table 3-4: Interrupt/Exception Table (Sheet 1 of 2) ................ 64 Table 3-5: List of Peripheral I/O Registers (Sheet 1 of 8) .............. 72 Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 1 of 25) ....
Page 20 Table 13-3: Status bits: Sa & Sb ....................446 Table 13-4: Programming modes ....................448 Table 13-5: Register Mapping of FVAN0 and FVAN1 ..............449 Table 13-6: Memory Map FVAN macro ..................450 Table 13-7: Retries ........................452 Table 13-8: System Diagnosis Clock Divider ................
Page 21: Chapter 1 Introduction
Chapter 1 Introduction 1.1 General The V850E/VANStorm single chip microcontroller, is a member of NEC’s V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in com- pact code size comparable to 16-bit CISC CPUs.
Page 22: Device Features
Chapter 1 Introduction 1.2 Device Features • - Core: V850E - Number of instructions: - Min. instruction execution time: 50 ns (@ f = 20 MHz) - General registers: 32 bits x 32 • Instruction set: - V850E (compatible with V850 plus additional powerful instructions for reducing code and increas- ing execution speed) - Signed multiplication (16 bits x 16 bits →...
Page 23: Application Fields
Chapter 1 Introduction • Full-CAN Interface: 1 channel • Full-VAN Interface: 2 channel • Timers - 16/32-bit multi purpose timer/event counter: 3 channel - 16-bit OS timer 2 channel - Watch timer: 1 channel - Watchdog timer: 1 channel ≤ 49 vectored interrupts •...
Page 24: Pin Configuration (Top View)
Chapter 1 Introduction 1.5 Pin Configuration (Top View) Figure 1-1: Pin Configuration of the VANStorm Microcontroller P30/TIE0/INTPE00 RX1VAN0 P31/TOE10/INTPE10 P32/TOE20/INTPE20 P11/CTXD1 P33/TOE30/INTPE30 P34//TOE40/INTPE40 P10/CRXD1 P35/TCLRE0/INTPE50 P25/SCK1 P40/TIE1/INTPE01 P24/SO1 P41/TOE11/INTPE11 P23/SI1 P42/TOE21/INTPE21 SS 54 P43/TOE31/INTPE31 DD 54 P44/TOE41/INTPE41 PP 1 P45/TCLRE1/INTPE51 P22/SCK0 P50/TIE2/INTPE02 P21/SO0...
Page 25 Chapter 1 Introduction Pin Identification A0 - A23 Address Bus RX0VAN0 - VAN Receive Data Inputs RX0VAN1 ANI0 - ANI11 Analogue Inputs RX1VAN0 - VAN Receive Data Inputs RX1VAN1 Power Supply +5 V RX2VAN0 - VAN Receive Data Inputs RX2VAN1 Analogue Reference Voltage RXD0 - Receive Data Inputs...
Page 26: Configuration Of Function Block
Chapter 1 Introduction 1.6 Configuration of Function Block 1.6.1 Block Diagram of VANStorm Figure 1-2: Block Diagram of the VANStorm Microcontroller power supply INT0 INT1 INTC INT2 CPU Core INTPE00-INTPE52 TIE0-TIE2 A0 - A23 16-/32-bit Barrel Hardware TCLRE0-TCLRE2 16-bit Shifter Flash/ Multiplier D0 - D15...
Page 27: On-Chip Units
Chapter 1 Introduction 1.6.2 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits → 32 bits or 32 bits x 32 bits →...
Page 28 Chapter 1 Introduction Serial interface (SIO) A 2-channel asynchronous serial interface (UART), 2-channel clocked serial interface (CSI), 2- channel FVAN and 1-channel FCAN are provided as serial interface. UART transfers data by using the TXDn and RXDn pins. (n = 0, 1) CSI transfers data by using the SOn, SIn, and SCKn pins.
Page 29: Chapter 2 Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non-port pins according to their functions. Port pins Port Function Alternate Port 1 CRXD1 7-bit input/output port...
Page 30 Chapter 2 Pin Functions Port Function Alternate Port 6 CCLK 6-bit input/output port INT0 INT1 INT2 RXD1 TXD1 PAL0-PAL15 Port AL A0-A15 16-bit input/output port PAH0-PAH7 Port AH A16-A23 8-bit input/output port PDL0- Port DL D0-D15 PDL15 16-bit input/output port PCS2-PCS4 Port CS CS2 - CS4...
Page 31 Chapter 2 Pin Functions Non-port pins Pin Name Function Alternate – Power supply 5 V DD50 DD54 – GND potential SS50 SS55 – Connection for external capacities Note 1 DD30 DD32 – GND potential SS30 SS32 Note 2 – Connection for external capacities to stabilize clock oscillator power supply input System clock oscillator connection pins.
Page 32 Chapter 2 Pin Functions Pin Name Function Alternate D0-D15 data bus of external bus PDL0-PDL15 A0-A7 output address bus of external bus PAL0-PAL7 A8-A15 PAL8-PAL15 A16-A23 PAH0-PAH7 output write strobe lower byte (bit 0-7) PCT0 write strobe upper byte (bit 8-15) PCT1 read strobe for external bus PCT4...
Page 33 Chapter 2 Pin Functions Pin related to VANStorm status Operating Status RESET RESET STOP WATCH IDLE HALT idle state (TI) ROMless D0 to D15 Hi-Z N.A. operate operate Hi-Z/-- Hi-Z/-- Hi-Z/-- A0 to A23 Hi-Z N.A. Hi-Z Hi-Z Hi-Z operate operate CS2 to CS4 Hi-Z...
Page 34: Description Of Pin Functions
Chapter 2 Pin Functions 2.2 Description of Pin Functions P10 to P17 (Port 1) … Input/output Port 1 is an 7-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P10 and P11 operate as serial inter- face (FCAN) input/output.
Page 35 Chapter 2 Pin Functions P20 to P27 (Port 2) … Input/output Port 2 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P20 to P27 operate as serial interface (CSI0, CSI1, UART0) input/output.
Page 36 Chapter 2 Pin Functions P30 to P35 (Port 3) … Input/output Port 3 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P30 to P35 operate as Real-time pulse unit (RPU) input/output and external interrupt request input.
Page 37 Chapter 2 Pin Functions P40 to P45 (Port 4) … Input/output Port 4 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P40 to P45 operate as Real-time pulse unit (RPU) input/output and external interrupt request input.
Page 38 Chapter 2 Pin Functions P50 to P55 (Port 5) … Input/output Port 5 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P50 to P55 operate as Real-time pulse unit (RPU) input/output and external interrupt request input.
Page 39 Chapter 2 Pin Functions P60 to P65 (Port 6) … Input Port 6 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input port, in control mode, P60 to P65 operate as external CAN clock supply, serial interface (UART1) input/output and external interrupt request input.
Page 40 Chapter 2 Pin Functions PAL0 to PAL15 (Port AL) … Input/output Port AL is an 16-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address bus (A0 to A15) when memory is expanded externally.
Page 41 Chapter 2 Pin Functions PAH0 to PAH7 (Port AH) … Input/output Port AH is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address bus (A16 to A23) when memory is expanded externally.
Page 42 Chapter 2 Pin Functions PDL0 to PDL15 (Port DL) … Input/output Port DL is a 16-/8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the data bus (D0 to D15) when memory is expanded externally.
Page 43 Chapter 2 Pin Functions (10) PCS2 to PCS4 (Port CS) … Input/output Port CS is a 3-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally.
Page 44 Chapter 2 Pin Functions (11) PCT0 to PCT4 (Port CT) … Input/output Port CT is a 5-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally.
Page 45 Chapter 2 Pin Functions (12) PCM0 to PCM1 (Port CM) … Input/output Port CM is a 2-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally.
Page 46 Chapter 2 Pin Functions (13) ANI00 to ANI11 (Analog input) … Input These are analog input pins to the A/D converter. (14) CLKSEL (Clock generator operating mode select) … Input This is the input pin that specifies the operation mode of the clock generator. Fix it so that the input level does not change during operation.
Page 47 Chapter 2 Pin Functions (22) CV (Power supply for clock generator) This is the positive power supply pin for the clock generator. (23) CV (Ground for clock generator) This is the ground pin for the clock generator. (24) V (Power supply) This is the positive power supply pin for the peripheral interface.
Page 48: Types Of Pin I/O Circuit And Connection Of Unused Pin
Chapter 2 Pin Functions 2.3 Types of Pin I/O Circuit and Connection of Unused Pin I/O Circuit Recommended Connection Type CRXD1 For input: individually connect to V or V via a resistor. CTXD1 For output: leave open. SCK0 SCK1 RXD0 TXD0 TIE0 INTPE00...
Page 49 Chapter 2 Pin Functions I/O Circuit Recommended Connection Type PAL0 For input: individually connect to V or V via a resistor. PAL1 For output: leave open. PAL2 PAL3 PAL4 PAL5 PAL6 PAL7 PAL8 PAL9 PAL10 PAL11 PAL12 PAL13 PAL14 PAL15 PAH0 PAH1 PAH2...
Page 50 Chapter 2 Pin Functions I/O Circuit Recommended Connection Type PDL0 For input: individually connect to V or V via a resistor. PDL1 For output: leave open. PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 RX2VAN0 individually connect to V or V...
Page 51: Figure 2-1: Pin I/O Circuits
Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 1 Type 2 P-ch N-ch Type 5-K Type 5 data data P-ch P-ch IN/OUT IN/OUT output output N-ch N-ch disable disable input input enable enable Type 19 Type 7 P-ch data N-ch N-ch...
Page 52 [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 53: Chapter 3 Cpu Function
Chapter 3 CPU Function The CPU of the V850E/ VANStorm is based on a RISC architecture and executes almost all the instruc- tions in one clock cycle, using a 5-stage pipeline control. 3.1 Features • Minimum instruction cycle: 50 ns (@ internal 20 MHz operation) •...
Page 54: Cpu Register Set
Chapter 3 CPU Function 3.2 CPU Register Set The registers of the V850E/ VANStorm can be classified into two categories: a general program register set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E1 User’s Manual Architecture. Figure 3-1: CPU Register Set (1) Program register set (2) System register set...
Page 55: Program Register Set
Chapter 3 CPU Function 3.2.1 Program register set The program register set includes general registers and a program counter. General registers Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Page 56: System Register Set
Chapter 3 CPU Function 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, use the system register load/store instruction (LDSR or STSR instruction) with a specific system register number indicated below. Table 3-2: System Register Numbers System Register Name Operand Specification...
Page 57: Figure 3-4: Program Status Word (Psw)
Chapter 3 CPU Function Figure 3-4: Program Status Word (PSW) After reset 00000020H Bit Position Flag Function 31 to 8 Reserved field (fixed to 0). Indicates that non-maskable interrupt (NMI) processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts. 0: NMI servicing not under execution.
Page 58: Operation Modes
Chapter 3 CPU Function Operation Modes 3.3.1 Operation modes The V850E/ VANStorm has the following operations modes. Mode specification is carried out by the MODE0 to MODE2 pins. Normal operation mode (a) Single-chip mode Access to the internal ROM is enabled. In single-chip mode, after system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruc- tion processing starts.
Page 59: Address Space
Chapter 3 CPU Function 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/ VANStorm is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 60: Image
Chapter 3 CPU Function 3.4.2 Image 64 MB physical address space is seen as 64 images in the 4 GB CPU address space. In actuality, the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address.
Page 61: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Function 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the PC (program counter), the higher 6 bits are set to “0”, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calcula- tion, the higher 6 bits ignore the carry or borrow.
Page 62: Memory Map
Chapter 3 CPU Function 3.4.4 Memory map The V850E/ VANStorm reserves areas as shown in Figure 3-9. Each mode is specified by the MODE0 to MODE2 pins. Figure 3-9: Memory Map Single-chip mode ROM-less mode 3FFFFFFH Internal peripheral Internal peripheral 4 Kbytes I/O area I/O area...
Page 63: Area
Chapter 3 CPU Function 3.4.5 Area Internal ROM area (a) Memory map 1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved. 256 KB are provided in the following addresses as physical internal ROM (flash memory). • Addresses 000000H to 03FFFFH (b) Interrupt/exception table The V850E/ VANStorm increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions.
Page 64: Table 3-4: Interrupt/Exception Table (Sheet 1 Of 2)
Chapter 3 CPU Function Table 3-4: Interrupt/Exception Table (Sheet 1 of 2) Start Address of Interrupt/ Interrupt/Exception Source Exception Table 00000000H RESET 00000010H NMIVC 00000020H NMIWDT 00000040H TRAP0n (n = 0 to F) 00000050H TRAP1n (n = 0 to F) 00000060H ILGOP/DBTRAP 00000080H...
Page 65 Chapter 3 CPU Function Table 3-4: Interrupt/Exception Table (Sheet 2 of 2) 000002E0H CAN1ERR 00000350H INTCSI0 00000360H INTCSI1 00000370H INTSER0 00000380H INTSR0 00000390H INTST0 000003D0H INTSER2 000003E0H INTSR2 000003F0H INTST2 00000450H INTFVAN0 00000460H INTFVAN1 Preliminary User’s Manual U14879EE1V0UM00...
Page 66: Figure 3-10: Internal Ram Area
Chapter 3 CPU Function Internal RAM area 12 KB of memory, addresses 3FFC000H to 3FFEFFFH, are reserved for the internal RAM area. In the µPD76F0018 the 8 KB of addresses 3FFC000H to 3FFDFFFH are provided as internal phys- ical RAM. Figure 3-10: Internal RAM Area µPD76F0018 3FFEFFFH...
Page 67: Figure 3-11: Internal Peripheral I/O Area
Chapter 3 CPU Function Internal peripheral I/O area 4 KB of memory, addresses 3FFF000H to 3FFFFFFH, is provided as an internal peripheral I/O area. Figure 3-11: Internal Peripheral I/O Area FFFFFFH Internal peripheral I/O area (4 Kbytes) FFF000H Peripheral I/O registers associated with the operation mode specification and the state monitoring for the internal peripherals I/O are all memory-mapped to the internal peripheral I/O area.
Page 68 Chapter 3 CPU Function External memory area The following areas can be used as external memory area. When in single-chip mode: 0100000H to 3FFBFFFH When in ROM-less mode:0000000H to 3FFBFFFH Access to the external memory area uses the chip select signal assigned to each memory block (which is carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0, CSC1)).
Page 69: External Memory Expansion
Chapter 3 CPU Function 3.4.6 External memory expansion By setting the port n mode control register (PMCn) to control mode, an external memory device can be connected to the external memory space using each pin of ports AL, AH, DL, CS, CT, and CM. Each register is set by selecting control mode for each pin of these ports using PMCn (n = AL, AH, DL, CS, CT, CM).
Page 70: Recommended Use Of Address Space
Chapter 3 CPU Function 3.4.7 Recommended use of address space The architecture of the V850E/ VANStorm requires that a register is utilized for address generation when accessing operand data in the data space. Operand data access from instruction can be directly executed at the address in this pointer register ±32 KB.
Page 71: Figure 3-13: Recommended Memory Map
Chapter 3 CPU Function Figure 3-13: Recommended Memory Map Data space FFFFFFFFH FFFFFA28H FFFFFA27H Internal peripheral I/O FFFFF000H FFFFEFFFH xFFFFFFFH Internal RAM xFFFFA28H FFFFC000H xFFFFA27H FFFFBFFFH Internal peripheral I/O xFFFF000H xFFFEFFFH xFFFE800H xFFFE7FFH Internal RAM xFFFC000H 04000000H xFFFFBFFFH 03FFFFFFH Internal Note peripheral I/O 03FFF000H...
Page 72: Peripheral I/O Registers
Chapter 3 CPU Function 3.4.8 Peripheral I/O registers Table 3-5: List of Peripheral I/O Registers (Sheet 1 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFF000H Port AL Undefined ×...
Page 73 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 2 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFF06AH Cache Configuration Register 0000H × × FFFF06EH System wait control register VSWC...
Page 74 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 3 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFF14AH Interrupt control register PIC29 × ×...
Page 75 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 4 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFF400H Port1 Undefined × × FFFF402H Port2 Undefined ×...
Page 76 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 5 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFF64CH Capture/Compare Control Register of CMSE120 0000H Subchannels 1 and 2 ×...
Page 77 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 6 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFF696H Primary Capture/Compare Register of CVPE21 0000H Subchannel 2 ×...
Page 78 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 7 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFF6E0H Capture/Compare Register of CVSE02 0000H Subchannel 0 ×...
Page 79 Chapter 3 CPU Function Table 3-5: List of Peripheral I/O Registers (Sheet 8 of 8) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFF90AH Shift register SIO0/ 0000H × SIOL0 ×...
Page 80: Programmable Peripheral I/O Registers
Chapter 3 CPU Function 3.4.9 Programmable peripheral I/O registers In the V850E/ VANStorm, the 16 KB area of x0000H to x3FFFH is provided as a programmable periph- eral I/O area. In this area, the area between x0000H and x0FFFH is used exclusively for the FCAN con- troller and the area between 0x1000 and 0x11FF is used exclusively for the two FVAN controllers.
Page 81: Figure 3-15: Peripheral Area Selection Control Register (Bpc)
Chapter 3 CPU Function Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. Figure 3-15: Peripheral Area Selection Control Register (BPC) Address Initial value BPC PA15 PA13 PA12 PA11 PA10 PA9 PA0 FFFFF064H 0000H Bit Position Bit Name Function PA15...
Page 82: Table 3-6: List Of Programmable Peripheral I/O Registers For The Fcan (Sheet 1 Of 25)
Chapter 3 CPU Function The list of the programmable peripheral I/O registers for the FCAN is shown below: Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 1 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit...
Page 83 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 2 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn04DH CAN message data register 025 M_DATA025 R/W Undefined xxxxn04EH...
Page 84 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 3 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn0A8H CAN message data register 050 M_DATA050 R/W Undefined xxxxn0A9H...
Page 85 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 4 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn0F5H CAN message status register 07 M_STAT07 Undefined xxxxn0F6H...
Page 86 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 5 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn14EH CAN message data register 106 M_DATA106 R/W Undefined xxxxn14FH...
Page 87 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 6 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn1A9H CAN message data register 131 M_DATA131 R/W Undefined xxxxn1AAH...
Page 88 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 7 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn1F6H CAN status set/cancel register 15 SC_STAT15 W 0000H xxxxn204H...
Page 89 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 8 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn24FH CAN message data register 187 M_DATA187 R/W Undefined xxxxn250H...
Page 90 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 9 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn2AAH CAN message data register 212 M_DATA212 R/W Undefined xxxxn2ABH...
Page 91 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 10 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn304H CAN message data length register 24 M_DLC24 Undefined xxxxn305H...
Page 92 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 11 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn350H CAN message ID register L26 M_IDL26 Undefined xxxxn352H...
Page 93 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 12 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn3ABH CAN message data register 293 M_DATA293 R/W Undefined xxxxn3ACH...
Page 94 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 13 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn405H CAN message control register 32 M_CTRL32 Undefined xxxxn406H...
Page 95 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 14 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn452H CAN message ID register H34 M_IDH34 Undefined xxxxn454H...
Page 96 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 15 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn4ACH CAN message data register 374 M_DATA374 R/W Undefined xxxxn4ADH...
Page 97 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 16 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn506H CAN message time stamp register 40 M_TIME40 Undefined xxxxn508H...
Page 98 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 17 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn554H CAN message configuration register 42 M_CONF42 R/W Undefined xxxxn555H CAN message status register 42...
Page 99 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 18 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn5ADH CAN message data register 455 M_DATA455 R/W Undefined xxxxn5AEH...
Page 100 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 19 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn608H CAN message data register 480 M_DATA480 R/W Undefined xxxxn609H...
Page 101 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 20 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn655H CAN message status register 50 M_STAT50 Undefined xxxxn656H...
Page 102 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 21 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn6AEH CAN message data register 536 M_DATA536 R/W Undefined xxxxn6AFH...
Page 103 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 22 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn709H CAN message data register 561 M_DATA561 R/W Undefined xxxxn70AH...
Page 104 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 23 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn756H CAN status set/cancel register 58 SC_STAT58 W 0000H xxxxn764H...
Page 105 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 24 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn7AFH CAN message data register 617 M_DATA617 R/W Undefined xxxxn7B0H...
Page 106 Chapter 3 CPU Function Table 3-6: List of programmable peripheral I/O registers for the FCAN (Sheet 25 of 25) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn812H CAN global interrupt enable register CGIE 0A00H Note...
Page 107: Table 3-7: List Of Programmable Peripheral I/O Registers For The Fvan (Sheet 1 Of 6)
Chapter 3 CPU Function The list of the programmable peripheral I/O registers for the FVAN is shown below: Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 1 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits...
Page 108 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 2 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxm02FH FVAN0 channel 3 register ID_MASK Undefined xxxxm030H...
Page 109 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 3 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxm05BH FVAN0 channel 9 register MESS_L/ Undefined xxxxm05EH FVAN0 channel 9 register...
Page 110 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 4 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxm104H FVAN1 Line status register 0x20H xxxxm105H FVAN1 transmit status register...
Page 111 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 5 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxm137H FVAN1 channel 4 register ID_MASK Undefined xxxxm138H...
Page 112 Chapter 3 CPU Function Table 3-7: List of programmable peripheral I/O registers for the FVAN (Sheet 6 of 6) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxm163H FVAN1 channel 10 register MESS_L/ Undefined xxxxm166H...
Page 113: Specific Registers
Chapter 3 CPU Function 3.5 Specific Registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the peripheral status register (PHS). The V850E/ VANStorm has three specific registers, the clock control register (CKC), the power save control register (PSC) and the power save mode register (PSM).
Page 114: Command Register (Prcmd)
Chapter 3 CPU Function 3.5.1 Command Register (PRCMD) This command register (PRCMD) is to protect the registers that may have a significant influence on the application system (PSC, PSM) from an inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 115: Peripheral Command Register (Phcmd)
Chapter 3 CPU Function 3.5.2 Peripheral Command Register (PHCMD) This command register (PHCMD) is to protect the registers that may have a significant influence on the application system (CKC) from an inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 116: Peripheral Status Register (Phs)
Chapter 3 CPU Function 3.5.3 Peripheral Status Register (PHS) The flag PRERR in the peripheral status register PHS indicates protection error occurrence. This register can be read/written in 8-bit units or bit-wise. Address At Reset PRERR FFFFF802H Protection error detection: If an incorrect write operation in a sequence without accessing the command register is performed to a protected internal register, the register is not written to, causing a protection error.
Page 117: Internal Peripheral Function Wait Control Register Vswc
Chapter 3 CPU Function 3.5.4 Internal peripheral function wait control register VSWC This register inserts wait states to the internal access of peripheral SFRs. This register can be read or written in 1-bit and 8-bit units. Address Reset Value VSWC SUWL2 SUWL1 SUWL0...
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Page 119: Chapter 4 Bus Control Function
Chapter 4 Bus Control Function The V850E/ VANStorm is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8 chip areas select function - 3 chip area select signals externally available (CS2 to CS4) •...
Page 120: Bus Control Pins
Chapter 4 Bus Control Function 4.2 Bus Control Pins The following pins are used for connecting to external devices. Bus Control Pin (Function when in Control Mode) Function when in Port Mode Register for Port/Control Mode Switching Data bus (D0 to D15) PDL0 to PDL15 (Port DL) PMCDL Address bus (A0 to A15)
Page 121: Memory Block Function
Chapter 4 Bus Control Function 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. Figure 4-1: Memory block function 3FFFFFFH 3FFFFFFH Block 15 Internal peripheral I/O area (4 Kbytes) (2 Mbytes) 3E00000H 3FFF000H...
Page 122: Chip Select Control Function
Chapter 4 Bus Control Function 4.3.1 Chip Select Control Function The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals. The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function.
Page 123 Chapter 4 Bus Control Function Figure 4-2: Chip Area Select Control Registers 0, 1 (2/2) Bit Position Bit Name Function 15 to 0 CSn0 to Chip Select CSn3 Enables chip select. (n = 0 to 7) CSnm CS Operation CS00 CS0 active during block 0 access CS01 CS0 active during block 1 access.
Page 124: Bus Cycle Type Control Function
Chapter 4 Bus Control Function 4.4 Bus Cycle Type Control Function In the V850E/ VANStorm, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O • Page ROM Bus cycle type configuration registers 0, 1 (BCT0, BCT1) The BCT0 and BCT1 registers specify the external devices and set whether operation is permitted for each CSn area (n = 0 to 7).
Page 125: Bus Access
Chapter 4 Bus Control Function 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-1: Number of Bus Access Clocks Resources (Bus width) Internal ROM Internal RAM Peripheral I/O External memory (32 bits)
Page 126: Endian Control Function
Chapter 4 Bus Control Function 4.5.3 Endian control function The endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal (CS2 to CS4).
Page 127: Figure 4-4: Big Endian Addresses Within Word
Chapter 4 Bus Control Function Figure 4-4: Big Endian Addresses within Word 24 23 16 17 0008H 0009H 000AH 000BH 0004H 0005H 0006H 0007H 0000H 0001H 0002H 0003H Figure 4-5: Little Endian Addresses within Word 24 23 16 17 000BH 000AH 0009H 0008H...
Page 128: Bus Width
Chapter 4 Bus Control Function 4.5.4 Bus width The V850E/ VANStorm accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower order side.
Page 129 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External Byte data External data bus data bus...
Page 130: Halfword Access (16 Bits)
Chapter 4 Bus Control Function Halfword access (16 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2...
Page 131 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 2 2n + 1 2n + 1 Halfword...
Page 132: Word Access (32 Bits)
Chapter 4 Bus Control Function Word access (32 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External...
Page 133 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus <4>...
Page 134 Chapter 4 Bus Control Function (b) When the bus width is 8 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 135 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 136 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Addres 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus data bus...
Page 137 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus <4>...
Page 138 Chapter 4 Bus Control Function (d) When the data bus width is 8 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 139 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 140: Wait Function
Chapter 4 Bus Control Function 4.6 Wait Function 4.6.1 Programmable wait function Data wait control registers 0, 1 (DWC0, DWC1) With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area. The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1) in programming.
Page 141 Chapter 4 Bus Control Function Address setup wait control register (ASC) The V850E/ VANStorm allows insertion of address setup wait states before the T1 cycle of the SRAM or page ROM cycle. The number of address setup wait states can be set with the ASC register for each CS area. This register can be read/written in 16-bit units Address Initial...
Page 142: External Wait Function
Chapter 4 Bus Control Function 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by the external wait pin (WAIT) to synchronize with the external device. Just as with programmable waits, access to internal ROM, internal RAM, and internal peripheral I/O areas cannot be controlled by external waits.
Page 143: Idle State Insertion Function
Chapter 4 Bus Control Function 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the cur- rent bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read access for each CS space.
Page 144: Bus Priority Order
Chapter 4 Bus Control Function 4.8 Bus Priority Order There are three external bus cycles: DMA cycle, operand data access, and instruction fetch. As for the priority order, the highest priority has the DMA cycle, instruction fetch, and operand data access, in this order.
Page 145: Boundary Operation Conditions
Chapter 4 Bus Control Function 4.9 Boundary Operation Conditions 4.9.1 Program space (1) Branching to the peripheral I/O area or successive fetch from the internal RAM area to the internal peripheral I/O area is inhibited. In terms of hardware, fetching the NOP op code continues, and fetching from the external memory is not performed.
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Page 147: Chapter 5 Memory Access Control Function
Chapter 5 Memory Access Control Function 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • Access to SRAM takes a minimum of 2 states. • Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers.
Page 148: Sram Connections
(a) When data bus width is 16 bits A1 to A17 A1 to A17 D0 to D15 D1 to D16 2-Mbit SRAM V850E/VANStorm (256 Kwords x 16 bits) (b) When data bus width is 8 bits A1 to A17 A0 to A16 D0 to D7...
Page 149: Sram, External Rom, External I/O Access
Chapter 5 Memory Access Control Function 5.1.3 SRAM, external ROM, external I/O access Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6) (a) During read CLKOUT (output) Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data...
Page 150 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (2/6) (b) During read (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data WAIT (input)
Page 151 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (3/6) (c) During write CLKOUT (output) Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data Data WAIT (input) Remarks: 1.
Page 152 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (4/6) (d) During write (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data WAIT (input)
Page 153 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (5/6) (e) When read → write operation CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data Data WAIT (input)
Page 154 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (6/6) (f) When write → read operation CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data Data D0 to D15 (I/O) WAIT (input) Remarks: 1.
Page 155: Page Rom Controller (Romc)
Chapter 5 Memory Access Control Function 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is provided for access to ROM (page ROM) with the page access function. Comparison of addresses with the immediately preceding bus cycle is carried out and wait control for normal access (off-page) and page access (on-page) is executed.
Page 156: Page Rom Connections
(a) In case of 16-bit data bus width A1 to A20 A0 to A19 D0 to D15 O1 to O16 V850E/VANStorm 16-Mbit page ROM (1 Mword x 16 bits) (b) In case of 8-bit data bus width A1 to A21...
Page 157: On-Page/Off
(b) In case of 16-Mbit (1 M × 16 bits) page ROM (8-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/VANStorm address output Page ROM address Off-page address On-page address Continuous reading possible: 16-bit data bus width × 8 words...
Page 158 (c) In case of 32-Mbit (2 M × 16 bits) page ROM (16-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/VANStorm address output Page ROM address Off-page address On-page address Continuous reading possible: 16-bit data bus width × 16 words...
Page 159: Page Rom Configuration Register (Prc)
Chapter 5 Memory Access Control Function 5.2.4 Page ROM configuration register (PRC) This register specifies whether page ROM on-page access is enabled or disabled. If on-page access is enabled, the masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the configuration of the page ROM being connected to and the number of bits that can be read con- tinuously, as well as the number of waits corresponding to the internal system clock, are set.
Page 160: Page Rom Access
Chapter 5 Memory Access Control Function 5.2.5 Page ROM access Figure 5-6: Page ROM Access Timing (1/4) (a) During read (when half word/word access with 8-bit bus width or when word access with 16-bit bus width) CLKOUT (output) Off-page address On-page address A0 to A23 (output) CSn (output)
Page 161 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (2/4) (b) During read (when byte access with 8-bit bus width or when byte/half word access with 16- bit bus width) CLKOUT (output) Off-page address On-page address A0 to A23 (output) CSn (output) RD (output) UWR (output)
Page 162 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (3/4) (c) During read (address setup wait, idle state insertion) (when half word/word access with 8- bit bus width or when word access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address...
Page 163 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (4/4) (d) During read (address setup wait, idle state insertion) (when byte access with 8-bit bus width or when byte/half word access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address On-page address...
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Page 165: Chapter 6 Interrupt/Exception Processing Function
Chapter 6 Interrupt/Exception Processing Function The V850E/ VANStorm is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 51 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 166: Table 6-1: Interrupt/Exception Source List (Sheet 1 Of 3)
Chapter 6 Interrupt/Exception Processing Function Table 6-1: Interrupt/Exception Source List (Sheet 1 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Reset Interrupt RESET – RESET input – 0000H 00000000H Undefined Non-maskable Interrupt...
Page 167 Chapter 6 Interrupt/Exception Processing Function Table 6-1: Interrupt/Exception Source List (Sheet 2 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Maskable Interrupt TINTCCE41/ PIC23 CC coincidence / Pin TimerE1/ 01F0H 000001F0H nextPC...
Page 168 Chapter 6 Interrupt/Exception Processing Function Table 6-1: Interrupt/Exception Source List (Sheet 3 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Maskable Interrupt Reserved PIC52 reserved 03C0H 000003C0H nextPC Interrupt INTSER1 PIC53...
Page 169: Non-Maskable Interrupts
Chapter 6 Interrupt/Exception Processing Function 6.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of V850E/ VANStorm are available for the following two requests: • NMI pin input (NMIVC) •...
Page 170: Operation
Chapter 6 Interrupt/Exception Processing Function 6.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code to the higher halfword (FECC) of ECR.
Page 171: Figure 6-2: Acknowledging Non-Maskable Interrupt Request
Chapter 6 Interrupt/Exception Processing Function Figure 6-2: Acknowledging Non-Maskable Interrupt Request (a) If a new NMIVC request is generated while an NMIVC service program is being executed Main routine (PSW.NP = 1) NMI request held pending because NMI request NMI request PSW.NP = 1 Pending NMI request processed (b) If a new NMIVC request is generated twice while an NMIVC service program is being...
Page 172: Figure 6-3: Example Of Non-Maskable Interrupt Request Acknowledgement Operation (1/2)
Chapter 6 Interrupt/Exception Processing Function Figure 6-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) (a) Multiple NMI requests generated at the same time NMIVC and NMIWD requests generated simultaneously Main routine NMIWD servicing NMIVC and NMIWD System reset requests (generated simultaneously) Preliminary User’s Manual U14879EE1V0UM00...
Page 173 Chapter 6 Interrupt/Exception Processing Function Figure 6-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (b) NMI request generated during NMI servicing NMI being NMI request generated during NMI servicing serviced NMIVC NMIWD • NMIVC request generated during • NMIWD request generated NMIVC NMIVC servicing during NMIVC servicing...
Page 174: Restore
Chapter 6 Interrupt/Exception Processing Function 6.2.2 Restore NMIVC Execution is restored from the non-maskable interrupt (NMIVC) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 175: Non-Maskable Interrupt Status Flag (Np)
Chapter 6 Interrupt/Exception Processing Function 6.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execu- tion. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 176: Edge Detection Function
Chapter 6 Interrupt/Exception Processing Function 6.2.4 Edge detection function The behaviour of the non-maskable-interrupt (NMIVC) can be specified by the voltage comparator mode register. The valid edge of the external NMI pin input can be specified by the EDN1, EDN0 bits, whereas the source has to be selected by the NSOCE bit.
Page 177: Maskable Interrupts
Chapter 6 Interrupt/Exception Processing Function 6.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/ VANStorm has 49 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 178: Figure 6-7: Maskable Interrupt Processing
Chapter 6 Interrupt/Exception Processing Function Figure 6-7: Maskable Interrupt Processing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 179: Restore
Chapter 6 Interrupt/Exception Processing Function 6.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 180: Priorities Of Maskable Interrupts
Chapter 6 Interrupt/Exception Processing Function 6.3.3 Priorities of maskable interrupts The V850E/ VANStorm provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 181: Figure 6-9: Example Of Processing In Which Another Interrupt Request Is Issued
Chapter 6 Interrupt/Exception Processing Function Figure 6-9: Example of Processing in Which Another Interrupt Request Is Issued While an Inter- rupt Is Being Processed (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 182 Chapter 6 Interrupt/Exception Processing Function Figure 6-9: Example of Processing in Which Another Interrupt Request Is Issued While an Inter- rupt Is Being Processed (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 183: Figure 6-10: Example Of Processing Interrupt Requests Simultaneously Generated
Chapter 6 Interrupt/Exception Processing Function Figure 6-10: Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are Processing of interrupt request b Interrupt request c (level 1) acknowledged first according to their priorities.
Page 184: Interrupt Control Register (Picn)
Chapter 6 Interrupt/Exception Processing Function 6.3.4 Interrupt control register (PICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the con- trol conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Figure 6-11: Interrupt Control Register (PICn) Address Initial...
Page 185: Table 6-2: Addresses And Bits Of Interrupt Control Registers (Sheet 1 Of 2)
Chapter 6 Interrupt/Exception Processing Function Table 6-2: Addresses and Bits of Interrupt Control Registers (Sheet 1 of 2) Address Register FFFFF110H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF112H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF114H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20 FFFFF116H PIC3...
Page 186 Chapter 6 Interrupt/Exception Processing Function Table 6-2: Addresses and Bits of Interrupt Control Registers (Sheet 2 of 2) Address Register FFFFF166H PIC43 FFFFF168H PIC44 FFFFF16AH PIC45 PIF45 PMK45 PPR452 PPR451 PPR450 FFFFF16CH PIC46 PIF46 PMK46 PPR462 PPR461 PPR460 FFFFF16EH PIC47 PIF47 PMK47 PPR472 PPR471 PPR470...
Page 187: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
Chapter 6 Interrupt/Exception Processing Function 6.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The PMKn bit of the IMR0 to IMR3 registers is equivalent to the PMKn bit of the PICn register. IMRm registers can be read/written in 16-bit units (m = 0 to 3).
Page 188: In-Service Priority Register (Ispr)
Chapter 6 Interrupt/Exception Processing Function 6.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an inter- rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 189: Noise Elimination Circuit
Chapter 6 Interrupt/Exception Processing Function 6.4 Noise Elimination Circuit V850E/ VANStorm is provided with filter / edge detection circuits for ports 3, 4, 5 and port 6 (3 chan- nels). The circuit consists from programmable digital filter, analog filter, edge detection and input source selection.
Page 190: Analog Filter
Chapter 6 Interrupt/Exception Processing Function Figure 6-16: Port Interrupt Input Circuit Overview Filter Digital Filter Frequencies Clock Clock 0 Clock 1 Clock 2 TINTCCEm0 from Timer E0 INTPn Analog to Interrupt Filter Edge Input INTPn Controller Detection EDGEM1, DFEN EDGEM0 Digital Filter FSMP1,...
Page 191: Interrupt Trigger Mode Selection
Chapter 6 Interrupt/Exception Processing Function The following figure illustrates the behaviour of the filter’s state machine. Figure 6-17: Digital Filter State Machine Diagram input = 0 & detect_enable = 1 Undisturbed RESET sequence input = 1 & detect_enable = 1 input = 0 Output = 0 input = 1...
Page 192: Filter Edge Detect Mode Register (Fem0N To Fem5N) For Timer E Input Pins
Chapter 6 Interrupt/Exception Processing Function 6.4.4 Filter Edge Detect Mode Register (FEM0n to FEM5n) for Timer E Input Pins (n=0 to 2) This registers are 8-bit register that control the filter function for the input interrupt pins INTPEmn and the Timer E input (TINEmn) (m=0 to 5, n=0 to 2). Additional they define the interrupt source and inter- rupt edge selection to the dedicated interrupt controller.
Page 193 Chapter 6 Interrupt/Exception Processing Function Figure 6-18: Timer E Input Pin Filter Edge Detect Mode Registers (FEM0n to FEM5n) (n=0 to 2) (2/2) Bit Name Description DFEN Digital filter enable Selects analog or digital filter for interrupt input. 0: Analog filter 1: Digital filter Note: Refer to Figure 6-15: “Timer E Input Circuit Overview”...
Page 194: Input Pins
Chapter 6 Interrupt/Exception Processing Function 6.4.5 Filter Edge Detect Mode Register (FEM0n to FEM5n) for INT0, INT1 and INT2 Input Pins This registers are 8-bit register that control the analog or digital filter function for the INT2 to INT0 inputs and the edge selection to the dedicated interrupt controller.
Page 195: Software Exception
Chapter 6 Interrupt/Exception Processing Function 6.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 6.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 196: Restore
Chapter 6 Interrupt/Exception Processing Function 6.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 197: Exception Status Flag (Ep)
Chapter 6 Interrupt/Exception Processing Function 6.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 6-22: Exception Status Flag (EP) 8 7 6 5 4 3 2 1 0 Initial value...
Page 198: Exception Trap
Chapter 6 Interrupt/Exception Processing Function 6.6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/ VANStorm, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is consid- ered as an exception trap.
Page 199: Figure 6-24: Restore Processing From Exception Trap
Chapter 6 Interrupt/Exception Processing Function Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 200: Debug Trap
Chapter 6 Interrupt/Exception Processing Function 6.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 201: Figure 6-26: Restore Processing From Debug Trap
Chapter 6 Interrupt/Exception Processing Function Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 202: Multiple Interrupt Processing Control
Chapter 6 Interrupt/Exception Processing Function 6.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 203 Chapter 6 Interrupt/Exception Processing Function Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register ← Exception such as TRAP instruction acknowl- • TRAP instruction edged.
Page 204: Interrupt Response Time
Chapter 6 Interrupt/Exception Processing Function 6.8 Interrupt Response Time The following table describes the V850E/ VANStorm interrupt response time (from interrupt generation to start of interrupt processing). Figure 6-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline) 5 system clocks CLKOUT Interrupt request Instruction 1 EX MEM WB...
Page 205: Periods In Which Interrupts Are Not Acknowledged
Chapter 6 Interrupt/Exception Processing Function 6.9 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. The interrupt request non-sampling instructions are as follows. •...
Page 206 Chapter 6 Interrupt/Exception Processing Function Preliminary User’s Manual U14879EE1V0UM00...
Page 207: Chapter 7 Clock Generator
Chapter 7 Clock Generator 7.1 Features • Multiplication function by PLL synthesizer: 4 x multiplication • Clock sources - Oscillation through oscillator connection - External clock input • Power save modes - Watch mode - HALT mode - IDLE mode - STOP mode •...
Page 208: Main System Clock Oscillator
Chapter 7 Clock Generator 7.3 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the X1 and X2 pins. Figure 7-2: Main system clock oscillator Preliminary User’s Manual U14879EE1V0UM00...
Page 209: Control Registers
Chapter 7 Clock Generator 7.4 Control Registers 7.4.1 Clock Control Register (CKC) This is a 8-bit register that controls the clock management. Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang-up.
Page 210: Pll Status Register (Pstat)
Chapter 7 Clock Generator Start-up after any Power-Save Mode condition recommendation It is recommended to proceed in the following way when performing power-save functions: 1. Switch off the PLL (PLLEN bit of CKC) 2. Wait for "PLL switch off status" by reading VBSTAT bit in PSTAT register. 3.
Page 211: Table 7-2: Relation System Clock To Resonator Frequency
Chapter 7 Clock Generator Available clock frequencies in the OSC mode Table 7-2: Relation system clock to resonator frequency System clock frequency (f System clock frequency (f Frequency of external resonator (f PLL On PLL Off 20.000 MHz 5.0000 MHz 5.0000 MHz 16.000 MHz 4.0000 MHz...
Page 212: Power Saving Functions
Chapter 7 Clock Generator 7.5 Power Saving Functions 7.5.1 General The device provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. Table 7-4: Power Saving Modes Overview Clock Source Mode Operation of...
Page 213: Figure 7-3: Power Save Mode State Transition Diagram
Chapter 7 Clock Generator Figure 7-3 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, WATCH mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 214: Table 7-5: Power Saving Mode Frequencies
Chapter 7 Clock Generator Table 7-5: Power Saving Mode Frequencies Clock Source Mode Operation of Clock Supply to oscillator peripherals watch/ watchdog prescaler Initial Status Normal – 4 MHz 4 MHz 4 MHz / mode PLL enabled Normal 16 MHz 16 MHz 4 MHz / watch mode/...
Page 215: Power Save Modes Outline
Chapter 7 Clock Generator 7.5.2 Power Save Modes Outline VANStorm is provided with the following standby modes: HALT, IDLE, WATCH, and software STOP. Application systems, which are designed so that these modes are switched appropriately according to operation purposes, reduce power consumption efficiently. HALT mode: In this mode supply of the operating clock to the CPU is stopped whereby other on-chip peripheral functions continue to operate.
Page 216: Halt Mode
Chapter 7 Clock Generator 7.5.3 HALT mode In this mode, the CPU clock is stopped, though the clock generators (oscillator and PLL synthesizer) continue to operate for supplying clock signals to other peripheral function circuits. Setting the HALT mode when the CPU is idle reduces the total system power consumption. In the HALT mode, program execution is stopped but the contents of all registers and internal RAM prior are retained as is.
Page 217: Table 7-7: Operation After Halt Mode Release By Interrupt Request
Chapter 7 Clock Generator HALT mode release: The HALT mode can be released by a non-maskable interrupt request, an unmasked maskable inter- rupt request, or RESET signal input. Release by interrupt request The HALT mode is released unconditionally by an unmasked maskable interrupt request regard- less of its priority level.
Page 218: Idle Mode
Chapter 7 Clock Generator 7.5.4 IDLE Mode In this mode, the CPU clock is stopped resulting in stop of the entire system, though the clock genera- tors (oscillator and PLL synthesizer) continue to operate. As it is not necessary to secure the oscillator oscillation stabilization time and the PLL lock-up time, it is possible to quickly switch to the normal operating mode in response to a release cause.
Page 219: Watch Mode
Chapter 7 Clock Generator 7.5.5 WATCH mode In this mode f clock is stopped while the oscillator continue to operate to achieve low power, though only oscillator & Watch/watchdog timer continue to operate. This mode compensates the HALT modes concerning the oscillator stabilization time and power con- sumption.
Page 220: Table 7-10: Operation After Watch Mode Release By Interrupt Request
Chapter 7 Clock Generator Watch mode release: The WATCH mode can be released by a non-maskable interrupt request, an unmasked maskable interrupt request, or RESET signal input. Release by interrupt request: The WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level.
Page 221: Software Stop Mode
Chapter 7 Clock Generator 7.5.6 Software STOP mode In this mode, the CPU clock is stopped including the clock generators (oscillator and PLL synthesizer), resulting in stop of the entire system for ultra-low power consumption (the only consumed is device leakage current).
Page 222: Register Description
Chapter 7 Clock Generator 7.6 Register Description 7.6.1 Power Save Control Register (PSC) This is an 8-bit register that controls the power save mode. Data can be written only in a sequence of specific instructions so that its contents are not easily rewrit- ten in case of program hang-up (refer to Chapter 3.5 “Specific Registers”...
Page 223 Chapter 7 Clock Generator Data is set in the power save control register (PSC) according to the following sequence. <1> Set the power save mode register (PSM) (with the following instructions). • Store instruction (ST/SST instruction) • Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <2>...
Page 224: Power Save Mode Register (Psm)
Chapter 7 Clock Generator 7.6.2 Power Save Mode Register (PSM) This is a 8-bit register that control the power save mode. This register can be read or written in 8- or 1-bit units. Address At Reset PSM1 PSM0 FFFFF820H Bit name Function PSM1, PSM0 Standby mode specification after STB bit (PSC.1) set to “1”.
Page 225: Securing Oscillation Stabilization Time
Chapter 7 Clock Generator 7.7 Securing Oscillation Stabilization Time 7.7.1 Oscillation stabilization time security specification Two methods can be used to secure the required stabilization times from when watch mode or software STOP mode is released. Securing the time using an on-chip time base counter Watch mode and software STOP mode are released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn).
Page 226: Figure 7-5: Stop Mode Release By Nmi Or Int
Chapter 7 Clock Generator Figure 7-5: STOP mode release by NMI or INT Set software STOP mode Oscillation waveform Internal main clock STOP state NMI (input) Note Oscillator is stopped Time base counter's counting time Note: Valid edge: When specified as the rising edge. The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance.
Page 227: Figure 7-6: Watch Mode Release By Reset Or Watchdog Timer
Chapter 7 Clock Generator Securing the time according to the signal level width (RESET pin input) Watch mode and software STOP mode are released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low level width of the signal that is input to the pin.
Page 228: Time Base Counter (Tbc)
Chapter 7 Clock Generator 7.7.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillator’s oscillation stabilization time when soft- ware STOP mode is released. It also is used to secure the flash stabilization time when software WATCH mode is released.
Page 229: Chapter 8 Timer / Counter (Real-Time Pulse Unit)
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.1 Timer D 8.1.1 Features (timer D) Timer D (TMD) functions as a 16-bit interval timer. 8.1.2 Function overview (timer D) • 16-bit interval timer: 2 channels • Compare registers: 2 • Count clock selected from divisions of internal system clock (maximum frequency of count clock: 10 MHz @ f = 20 MHz) •...
Page 230: Basic Configuration
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.1.3 Basic configuration Table 8-1: Timer D Configuration List Timer Count Clock Register R/W Generated Capture Timer Other Interrupt Trigger Output S/R Functions Signal Timer D TMD0 – – – – /16, /32, /64, CMD0...
Page 231: Figure 8-2: Timer D Registers 0, 1 (Tmd0, Tmd1)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timers D Registers 0, 1 (TMD0, TMD1) TMDn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0, 1). Starting and stopping TMDn is controlled by the CE bit of the timer D control register n (TMCDn). A division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 232: Figure 8-3: Timer D Compare Registers 0, 1 (Cmd0 To Cmd1)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer D compare registers 0, 1 (CMD0 to CMD1) CMDn and the TMDn register count value are compared, and an interrupt request signal (TINTCMDn) is generated when a match occurs. TMDn is cleared, synchronized with this match. If the CAE bit of the TMCDn register is set to 0, a reset is performed asynchronously, and the regis- ters are initialized (n = 0, 1).
Page 233: Figure 8-4: Example Of Timing During Tmd Operation
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-4: Example of Timing During TMD Operation (a) When TMDn < CMDn TMDn CMDn TINTCMDn (b) When TMDn > CMDn TMDn FFFFH CMDn INTCMDn Remarks: 1. p = TMDn value when overwritten 2.
Page 234: Control Register
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.1.4 Control register Timer D control registers 0, 1 (TMCD0 to TMCD1) The TMCDn register controls the operation of timer D (n = 0, 1). This register can be read/written in 8- or 1-bit units. Figure 8-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1) Address In iti al val ue...
Page 235: Operation
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.1.5 Operation Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is compared with the TMDn count value (n = 0, 1). If a match is detected by the compare operation, an interrupt (TINTCMDn) is generated.
Page 236: Application Example
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-6: TMD Compare Operation Example (2/2) (b) When CMDn is set to 0 Count clock Count up TMDn clear Clear TMDn FFFFH CMDn Match detected (TINTCMDn) Overflow Remark: Interval time = (FFFFH + 2) × Count clock cycle 8.1.6 Application example Interval timer This section explains an example in which timer D is used as an interval timer with 16-bit precision.
Page 237: Precautions
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.1.7 Precautions Various precautions concerning timer D are shown below. (1) To operate TMDn, first set (1) the CAE bit of the TMCDn register. (2) Up to f /2 clocks are required after a value is set in the CE bit of the TMCDn register until the set value is transferred to internal units.
Page 238: Timer E
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.2 Timer E 8.2.1 Features (timer E) The 3 x 6 channels 16/32-bit multi purpose timers En (TMEn) (n = 0 to 2) operate as • Pulse interval and frequency measurement counter •...
Page 239 Chapter 8 Timer / Counter (Real-time Pulse Unit) Note 3, Note 5 Note 2 • Up/down count control with external pin input - Up/down count operation in the compare mode can be controlled with the TCLREn pin input sig- nal. •...
Page 240: Basic Configuration
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.2.3 Basic configuration The basic configuration is shown below. Table 8-2: Timer E Configuration List Timer Count Clock Register Generated Capture Trigger Note 1 Other Timer Output Interrupt Functions Signal Timer TBASE0n –...
Page 241: Figure 8-7: Block Diagram Of Timer E
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-7: "Block Diagram of Timer E" shows the block diagram of one timer E unit. Figure 8-7: Block Diagram of Timer E CSEn CNT = MAX. TINTOVE0n ECLR 1/2, 1/4, 1/8, 1/16, TBASE0n CNT = 0 TCOUNTE0...
Page 242: Table 8-3: Meaning Of Signals In Block Diagram
Chapter 8 Timer / Counter (Real-time Pulse Unit) Table 8-3: Meaning of Signals in Block Diagram Signal Name Meaning Note 1 TBASE1n count signal input in 32-bit mode CASC Count value of timer En (CNT = MAX.: Maximum value count signal output of timer En (generated when TBASE0n, TBASE1n = FFFFH), CNT = 0: Zero count signal output of timer (generated when TBASE0n, TBASE1n = 0000H)) TBASE0n, TBASE1n count signal input in 16-bit mode...
Page 243: Figure 8-8: Timer E Time Base Counter 0 Registers 0 To 2 (Tbase00 To Tbase02)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E time base counters 0, 1 registers 0 to 2 (TBASE0n, TBASE1n (n = 0 to 2)) The features of time base counters TBASE0n, TBASE1n are listed below. • Free-running counter that enables counter clearing by compare match of sub-channel 0 and sub- channel 5 •...
Page 244: Figure 8-10: Timer E Sub-Channel 0 Capture/Compare Registers 0 To 2 (Cvse00 To 02)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel 0 capture/compare registers 0 to 2 (CVSE00 to CVSE02) The CVSE0n register is the 16-bit sub-channel 0 capture/compare register of timer TMEn (n = 0 to 2). In the capture register mode, it captures the TBASE0n count value. In the compare register mode, it detects match with TBASE0n.
Page 245: Figure 8-11: Timer E Sub-Channel X Main Capture/Compare Registers 0 To 2 (Cvpex0 To Cvpex2) (X = 1 To 4)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel x main capture/compare registers 0 to 2 (CVPEx0 to CVPEx2) (x = 1 to 4) The CVPExn register is a 16-bit sub-channel x main capture/compare register of timer TMEn (x = 1 to 4) (n = 0 to 2).
Page 246: Figure 8-12: Timer E Sub-Channel X Sub Capture/Compare Registers 0 To 2 (Cvsex0 To Cvsex2) (X = 1 To 4)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel x sub capture/compare registers 0 to 2 (CVSEx0 to CVSEx2) (x = 1 to 4) The CVSExn register is a 16-bit sub channel x sub-capture/compare register of timer TMEn (x = 1 to 4) (n = 0 to 2).
Page 247: Figure 8-13: Timer E Sub-Channel 5 Capture/Compare Registers (Cvse50 To Cvse52)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel 5 capture/compare registers 0 to 2 (CVSE50 to CVSE52) The CVSE5n register is the 16-bit sub-channel 5 capture/compare register of timer TMEn (n = 0 to In the capture register mode, it captures the count value of TBASE1n. In the compare register mode, it detects match with TBASE1n.
Page 248: Control Registers
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.2.4 Control Registers Timer E clock stop registers 0 to 2 (STOPTE0 to STOPTE2) The STOPTEn register is used to stop the operation clock input to timer TMEn (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 249: Figure 8-15: Timer E Count Clock/Control Edge Selection Registers 0 To 2 (Cse0 To Cse2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E count clock/control edge selection registers 0 to 2 (CSE0 to CSE2) The CSEn register is used to specify the timer TMEn count clock and the control valid edge (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 250: Figure 8-16: Timer E Sub-Channel Input Event Edge Selection Register 0 To 2 (Sese0 To Sese2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel input event edge selection registers 0 to 2 (SESE0 to SESE2) The SESEn register specifies the valid edge of the external capture signal input (TIExn) for the sub- channel x capture/compare register performing capture (x = 0 to 5, n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 251: Figure 8-17: Timer E Time Base Control Registers 0 To 2 (Tcre0 To Tcre2) (1/2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E time base control registers 0 to 2 (TCRE0 to TCRE2) The TCREn register controls the operation of timer TMEn (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units. Figure 8-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (1/2) Initial Address...
Page 252 Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (2/2) Bit Position Bit Name Function 11, 3 ECEEy Specifies TBASEyn count operation enable/disable through ECLR signal input. 0: Don’t enable TBASEyn count operation 1: Enable TBASEyn count operation Cautions: 1.
Page 253: Figure 8-18: Timer E Output Control Registers 0 To 2 (Octle0 To Octle2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E output control registers 0 to 2 (OCTLE0 to OCTLE2) The OCTLEn register controls timer output from the TOExn pin (x = 1 to 4, n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units. Figure 8-18: Timer E Output Control Registers 0 to 2 (OCTLE0 to OCTLE2) Initial Address...
Page 254: Figure 8-19: Timer E Sub-Channel 0, 5 Capture/Compare Control Registers 0 To 2 (Cmse050 To Cmse052)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel 0, 5 capture/compare control registers 0 to 2 (CMSE050 to CMSE052) The CMSE05n register controls timer TMEn sub-channel 0 capture/compare register (CVSE0n) and timer TMEn sub-channel 5 capture/compare register (CVSE5n) (n = 0 to 2). This register can be read/written in 16-bit units.
Page 255: Figure 8-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 To 2 (Cmse120 To Cmse122) (1/2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel 1, 2 capture/compare control register 0 to 2 (CMSE120 to CMSE122) The CMSE12n register controls the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 1, 2) (n = 0 to 2).
Page 256 Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 to 2 (CMSE120 to CMSE122) (2/2) Bit Position Bit Name Function 11, 3 LNKEx Selects capture event signal input from edge selection and specifies transfer opera- tion in compare register mode.
Page 257: Figure 8-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 To 2 (Cmse340 To Cmse342) (1/2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E sub-channel 3, 4 capture/compare control registers 0 to 2 (CMSE340 to CMSE342) The CMSE34n register controls the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 3, 4) (n = 0 to 2).
Page 258 Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2 (CMSE340 to CMSE342) (2/2) Bit Position Bit Name Function 11, 3 LNKEx Selects capture event signal input from edge selection and specifies transfer opera- tion in compare register mode.
Page 259: Figure 8-22: Timer E Time Base Status Register (Tbstate0 To Tbstate2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) Timer E time base status registers 0 to 2 (TBSTATE0 to TBSTATE2) The TBSTATEn register indicates the status of the time base counter TBASEyn (y = 0, 1) (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 260: Figure 8-23: Timer E Capture/Compare Status Registers 0 To 2 (Ccstate0 To Ccstate2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) (10) Timer E capture/compare status registers 0 to 2 (CCSTATE0 to CCSTATE2) The CCSTATEn register indicates the status of the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 1 to 4) (n = 0 to 2).
Page 261: Figure 8-24: Timer E Output Delay Registers 0 To 2 (Odele0 To Odele2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) (11) Timer E output delay registers 0 to 2 (ODELE0 to ODELE2) The ODELEn register sets the output delay operation synchronized with the clock to the TOExn pin’s output delay circuit (x = 1 to 4) (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 262: Figure 8-25: Timer E Software Event Capture Registers 0 To 2 (Csce0 To Csce2)
Chapter 8 Timer / Counter (Real-time Pulse Unit) (12) Timer E software event capture registers 0 to 2 (CSCE0 to CECE2) The CSCE0n register sets capture operation by software in the capture register mode (n = 0 to 2). This register can be read/written in 16-bit units. Figure 8-25: Timer E Software Event Capture Registers 0 to 2 (CSCE0 to CSCE2) Initial Address...
Page 263: Operation
Chapter 8 Timer / Counter (Real-time Pulse Unit) 8.2.5 Operation Edge detection The edge detection timing is shown below. Figure 8-26: Edge Detection Timing Note TIEx, TCLREn, TCOUNTEy MUXTB0 ED1, ED2 ECLR Note: The set values of the TESyE1, TESyE0 bits and the CESE1, CESE0 bits of the CSEn register, and the IESEx1, IESEx0 bits of the SESEn register are shown.
Page 264: Figure 8-27: Timer E Up Count Timing
Chapter 8 Timer / Counter (Real-time Pulse Unit) Basic operation of timer E Figures 8-27 to 8-30 show the basic operation of timer E. Figure 8-27: Timer E Up Count Timing (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, ECEEy Bit = 0, ECREy Bit = 0, CLREy Bit = 0, CASE1 Bit = 0) Note 1 OSTEy...
Page 265: Figure 8-28: External Control Timing Of Timer E
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-28: External Control Timing of Timer E (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 0) Note ECEEy Note ECREy Note CLREy ECLR...
Page 266: Figure 8-29: Operation In Timer E Up/Down Count Mode
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-29: Operation in Timer E Up/Down Count Mode (When TCREn Register’s ECEEy bit = 0, ECREy Bit = 0, CLREy Bit = 0, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 0) Note 1 UDSEy1, UDSEy0 don't care...
Page 267: Figure 8-30: Timer E Timing In 32-Bit Cascade Operation Mode
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-30: Timer E Timing in 32-Bit Cascade Operation Mode (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, ECEEy Bit = 0, ECREy Bit = 0, CLREy Bit = 0, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 1) Note CASC CNT [TB0]...
Page 268: Figure 8-31: Block Diagram Of Timer E Multiplex Count Generation Circuit
Chapter 8 Timer / Counter (Real-time Pulse Unit) Operation of capture/compare register (sub-channels 1 to 4) Sub-channels 1 to 4 receive the count value of the timer TMEn multiplex count generation circuit (n = 0 to 2). The multiplex count generation circuit is an internal unit of the time base counters TBASE0n, TBASE1n that supplies the multiplex count value MUXCNT to sub-channels 1 to 4.
Page 269: Figure 8-32: Timer E Multiplex Count Timing
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-32: Timer E Multiplex Count Timing CNT (TB0) FFFEH FFFFH 0000H 0001H 1234H 1235H CNT (TB1) MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H...
Page 270: Figure 8-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEx Bit of CMSEmn Register, and CMSEmn Register’s CCSEx Bit = 0, BFEEx Bit = 0, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) MUXTB0 MUXTB1...
Page 271: Figure 8-34: Timer E Capture Operation: Mode With 16-Bit Buffer
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-34: Timer E Capture Operation: Mode with 16-Bit Buffer (When CMSEmn Register’s TB1Ex Bit = 0, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = 1, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) MUXTB0 MUXTB1 MUXCNT...
Page 272: Figure 8-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode (When CMSEmn Register’s TB1Ex Bit = 1, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = Arbitrary, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) TCOUNTE0 = TCOUNTE1 CNT (TB0)
Page 273: Figure 8-36: Timer E Capture Operation: Capture Control By Software And Trigger Timing
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-36: Timer E Capture Operation: Capture Control by Software and Trigger Timing (When CMSEmn Register’s TB1Ex Bit = 0, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = 1) MUXTB0 MUXTB1...
Page 274: Figure 8-37: Timer E Compare Operation: Buffer-Less Mode
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-37: Timer E Compare Operation: Buffer-Less Mode (When CMSEmn Register’s CCSEx Bit = 1, LNKEx Bit = Arbitrary, BFEEx Bit = 0) MUXTB0 MUXTB1 MUXCNT Note 1 TB0Ex Note 1 TB1Ex WRITE_ENABLE_S RELOAD_PRIMARY CVSExn register...
Page 275: Figure 8-38: Timer E Compare Operation: Mode With Buffer
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-38: Timer E Compare Operation: Mode with Buffer (When CMSEmn Register’s CCSEx Bit = 1, BFEEx Bit = 1, and Operation Is Delayed Through Setting of LNKEx Bit) MUXTB0 MUXTB1 MUXCNT Note LNKEx WRITE_ENABLE_S...
Page 276: Figure 8-39: Timer E Capture Operation: Count Value Read Timing
Chapter 8 Timer / Counter (Real-time Pulse Unit) Operation of capture/compare register (sub-channels 0, 5) Figures 8-39 and 8-40 show the operation of the capture/compare register (sub-channels 0, 5). Figure 8-39: Timer E Capture Operation: Count Value Read Timing (When CMSE05n Register’s CCSEx Bit = 0, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) Note 1 LNKEx...
Page 277: Figure 8-40: Timer E Compare Operation: Timing Of Compare Match And Write Operation To Register
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-40: Timer E Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE05n Register’s CCSEx Bit = 1, EEVEx Bit = Arbitrary, and CSCE0n Register’s SEVEx Bit = Arbitrary, and TCRLn Register’s UDSEy1 Bit = 0, UDSEy0 Bit = 0) CPU write C/C CVSExn register MATCH...
Page 278: Figure 8-41: Timer E Signal Output Operation: Toggle Mode 0 And Toggle Mode 1
Chapter 8 Timer / Counter (Real-time Pulse Unit) Operation of output circuit Figures 8-41 to 8-44 show the output circuit operation. Figure 8-41: Timer E Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLEn Register’s SWFEx Bit = 0, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note OTMEx1, OTMEx0...
Page 279: Figure 8-42: Timer E Signal Output Operation: Toggle Mode 2 And Toggle Mode 3
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-42: Timer E Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLEn Register’s SWFEx Bit = 0, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note OTMEx1, OTMEx0 bits TOExn timer output Note (ALVEx = 0...
Page 280: Figure 8-43: Timer E Signal Output Operation: During Software Control
Chapter 8 Timer / Counter (Real-time Pulse Unit) Figure 8-43: Timer E Signal Output Operation: During Software Control (When OCTLEn Register’s OTMEx1, OTMEx0 Bits = Arbitrary, SWFEx Bit = 1, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note ALVEx TOExn timer output Note: ALVEx bit of OCTLEn register...
Page 281: Chapter 9 Watch Timer
Chapter 9 Watch Timer 9.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 9-1shows the block diagram of the watch timer. Figure 9-1: Block Diagram of Watch Timer Clear 5-bit counter...
Page 282: Configuration
Chapter 9 Watch Timer Watch timer The watch timer generates an interrupt request (INTWT) at time intervals of 512 µs or 2.097 s by using the subsystem clock f or f or the derived 11-bit prescaler clock from f CKSEL1 CKSEL2 CKSEL1 (refer to Figure 7-1: “Block Diagram of the Clock Generator”...
Page 283: Watch Timer Control Register
Chapter 9 Watch Timer 9.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer. Watch timer mode control register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 284: Figure 9-2: Watch Timer Mode Control Register (Wtm)
Chapter 9 Watch Timer Figure 9-2: Watch Timer Mode Control Register (WTM) Address After Reset WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 FFFFF560H R/W WTM6 WTM5 WTM4 Selects Interval Time of Prescaler (f = 4 MHz) (2.408 ms, 512 µs) (4.096 ms, 1.024 ms) (8.192 ms, 2.048 ms) (16.384 ms, 4.096 ms)
Page 285: Operations
Chapter 9 Watch Timer 9.4 Operations 9.4.1 Operation as watch timer Note The watch timer operates with time intervals from 2.09715 s to 512 µs with fw of 31250 Hz / 7812.5 Hz. The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTM0) and 1 (WTM1) of the watch timer mode control register (WTM) are set to 1.
Page 286: Figure 9-3: Operation Timing Of Watch Timer/Interval Timer
Chapter 9 Watch Timer Figure 9-3: Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Note Note Interrupt time of watch timer Interrupt time of watch timer Interval timer interrupt INTWTI Interval time (T) Interval time (T) Notes:...
Page 287: Chapter 10 Watchdog Timer
Chapter 10 Watchdog Timer 10.1 Features: • Generates reset or NMI (selectable) • Have to be started once by software control (afterwards protected) • Will operate at system frequency divided by 4 to get a lower watch limit of 1ms. Figure 10-1: Block Diagram of Watchdog Timer Unit CKSEL1 Watchdog Timer...
Page 288: Control Register
Chapter 10 Watchdog Timer 10.3 Control Register 10.3.1 Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. This register sets the overflow times of the watchdog timer. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H.
Page 289: Operation
Chapter 10 Watchdog Timer 10.4 Operation 10.4.1 Operating as watchdog timer Set bit 6 (WDTM) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect program runaway and generate an RESET signal. Setting bit 7 (WDTEN) of WDTM to 1 starts the count. After counting starts, if WDTEN is set to 1 again within the set time interval for runaway detection, the watchdog timer is cleared and counting starts again.
Page 290 [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 291: Chapter 11 Serial Interface Function
Chapter 11 Serial Interface Function 11.1 Features The serial interface function provides four types of serial interfaces combining a total of seven transmit/ receive channels. All channels can be used simultaneously. The four interface formats are as follows. (1) Asynchronous serial interfaces (UART0, UART1): 2 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels (3) FCAN controller: 1 channels (4) FVAN controller: 2 channels...
Page 292: Asynchronous Serial Interfaces 0, 1 (Uart0, Uart1)
Chapter 11 Serial Interface Function 11.2 Asynchronous Serial Interfaces 0, 1 (UART0, UART1) 11.2.1 Features • Transfer rate: 300 bps to 625 Kbps (using a dedicated baud rate generator and an internal system clock of 20 MHz) • Full-duplex communications - On-chip reception buffer register (RXBn) - On-chip transmission buffer register (TXBn) •...
Page 293: Configuration
Chapter 11 Serial Interface Function 11.2.2 Configuration UARTn is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface status register (ASISn), and asynchronous serial interface transmission status register (ASIFn). Receive data is maintained in the reception buffer register (RXBn), and transmit data is written to the transmission buffer register (TXBn).
Page 294: Figure 11-1: Asynchronous Serial Interfaces 0, 1 Block Diagram
Chapter 11 Serial Interface Function Transmission buffer registers 0, 1 (TXB0, TXB1) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame.
Page 295: Control Registers
Chapter 11 Serial Interface Function 11.2.3 Control registers Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read/written in 8 bit or 1-bit units (n = 0, 1). Figure 11-2: Asynchronous Serial Interface Mode Registers 0, 1 (ASIM0, ASIM1) (1/3) Address Initial...
Page 296 Chapter 11 Serial Interface Function Figure 11-2: Asynchronous Serial Interface Mode Registers 0, 1 (ASIM0, ASIM1) (2/3) Bit Position Bit Name Function Enables/disables reception. 0: Disable reception (Perform synchronous reset of reception circuit) 1: Enable reception Cautions: 1. Set the RXE bit to 1 after setting the CAE bit to 1 when starting transfer.
Page 297 Chapter 11 Serial Interface Function Figure 11-2: Asynchronous Serial Interface Mode Registers 0, 1 (ASIM0, ASIM1) (3/3) Bit Position Bit Name Function 4, 3 PS1, PS0 • 0 parity During transmission, the parity bit is cleared (0) regardless of the transmit data.
Page 298: Figure 11-3: Asynchronous Serial Interface Status Registers 0, 1 (Asis0, Asis1)
Chapter 11 Serial Interface Function Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) The ASISn register, which consists of 3-bit error flags (PE, FE and OVE), indicates the error status when UARTn reception is completed. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 299: Figure 11-4: Asynchronous Serial Interface Transmit Status Registers 0, 1 (Asif0, Asif1)
Chapter 11 Serial Interface Function Asynchronous serial interface transmission status registers 0, 1 (ASIF0, ASIF1) The ASIFn register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 300: Figure 11-5: Reception Buffer Registers 0, 1 (Rxb0, Rxb1)
Chapter 11 Serial Interface Function Reception buffer registers 0, 1 (RXB0, RXB1) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. When reception is enabled (RXE bit = 1 in the ASIMn register), receive data is transferred from the reception shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 301: Figure 11-6: Transmission Buffer Registers 0, 1 (Txb0, Txb1)
Chapter 11 Serial Interface Function Transmission buffer registers 0, 1 (TXB0, TXB1) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE bit = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn register.
Page 302: Interrupt Requests
Chapter 11 Serial Interface Function 11.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0 and UART1. • Reception error interrupt (INTSERn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt (n = 0, 1).
Page 303: Operation
Chapter 11 Serial Interface Function 11.2.5 Operation Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 11-7. The character bit length within one data frame, the type of parity, and the stop bit length are speci- fied according to the asynchronous serial interface mode register (ASIMn) (n = 0, 1).
Page 304: Figure 11-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing
Chapter 11 Serial Interface Function Transmit operation When CAE bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin. Then, when TXE bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register (TXBn) (n = 0, 1).
Page 305: Table 11-2: Transmission Status And Whether Or Not Writing Is Enabled
Chapter 11 Serial Interface Function Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the time that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by con- tinuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame.
Page 306: Figure 11-9: Continuous Transmission Starting Procedure
Chapter 11 Serial Interface Function (a) Starting procedure Figure 11-9 shows the procedure to start continuous transmission. Figure 11-9: Continuous Transmission Starting Procedure TXDn Start Parity Start Parity Data (1) Stop Data (2) Stop (output) INTSTn (output) TXBn Data (1) Data (2) Data (3) register...
Page 307: Figure 11-10: Continuous Transmission End Procedure
Chapter 11 Serial Interface Function (b) Ending procedure Figure 11-10: Continuous Transmission End Procedure TXDn Data Data (n − 1) Parity Start Parity Start Parity Stop Stop Data (n) Stop (n − 2) (output) INTSTn (output) TXBn Data (n − 1) Data (n) register Transmission...
Page 308: Figure 11-11: Asynchronous Serial Interface Reception Completion Interrupt Timing
Chapter 11 Serial Interface Function Receive operation An awaiting reception state is set by setting CAE bit to 1 in the ASIMn register and then setting RXE bit to 1 in the ASIMn register. To start a receive operation, detects a start bit first. The start bit is detected by sampling RXDn pin.
Page 309: Figure 11-12: When Reception Error Interrupt Is Separated From Intsrn Interrupt (Isrm Bit = 0)
Chapter 11 Serial Interface Function Reception error The three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. The data reception result is that the various flags of the ASISn register are set (1), and a reception error interrupt (INTSERn) or a reception completion interrupt (INTSRn) is gener- ated at the same time.
Page 310 Chapter 11 Serial Interface Function Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity -During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 311: Figure 11-14: Noise Filter Circuit
Chapter 11 Serial Interface Function Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output basic clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sam- pled as input data.
Page 312: Dedicated Baud Rate Generators (Brg) Of Uartm (M = 0, 1)
Chapter 11 Serial Interface Function 11.2.6 Dedicated baud rate generators (BRG) of UARTm (m = 0, 1) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UARTn (n = 0, 1). The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 313: Figure 11-17: Clock Select Registers 0, 1 (Cksr0 To Cksr1)
Chapter 11 Serial Interface Function Serial clock generation A serial clock can be generated according to the settings of the CKSRm and BRGCm registers. The basic clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSRm register.
Page 314: Figure 11-18: Baud Rate Generator Control Registers 0, 1 (Brgc0, Brgc1)
Chapter 11 Serial Interface Function (b) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) The BRGCm register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit or 1-bit units (m = 0, 1). Figure 11-18: Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1) Address Initial...
Page 315 Chapter 11 Serial Interface Function (c) Baud rate The baud rate is the value obtained according to the following formula. Baud rate 2 k ⋅ = Frequency [Hz] of basic clock selected according to TPS3 to TPS0 bits of CKSRm register.
Page 316: Table 11-4: Baud Rate Generator Setting Data
Chapter 11 Serial Interface Function (e) Baud rate setting example Table 11-4: Baud Rate Generator Setting Data = 20 MHz = 16 MHz = 5 MHz = 4 MHz Baud Rate [bps] /256 /256 0.16 0.16 0.16 0.16 /128 /128 0.16 0.16 0.16...
Page 317: Figure 11-19: Allowable Baud Rate Range During Reception
Chapter 11 Serial Interface Function Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution: The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 318: Table 11-5: Maximum And Minimum Allowable Baud Rate Error
Chapter 11 Serial Interface Function When the latch timing margin is made 2 basic clocks (Clock), the minimum allowable transfer rate (FLmin) is as follows. – × × × FLmin 11 FL ------------------- – Therefore, the transfer destination’s maximum baud rate (BRmax) that can be received is as fol- lows.
Page 319: Precautions
Chapter 11 Serial Interface Function Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of basic clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 320: Clocked Serial Interfaces 0, 1 (Csi0, Csi1)
Chapter 11 Serial Interface Function 11.3 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 11.3.1 Features • High-speed transfer: Maximum 5 Mbps • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits • Transfer data direction can be switched between MSB first and LSB first •...
Page 321: Configuration
Chapter 11 Serial Interface Function 11.3.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed with reading SIOn register (n = 0, 1). Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn.
Page 322: Figure 11-21: Block Diagram Of Clocked Serial Interfaces
Chapter 11 Serial Interface Function (12) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat trans- fer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock control circuit Controls the serial clock supply to the shift register.
Page 323: Control Registers
Chapter 11 Serial Interface Function 11.3.3 Control registers Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSIn operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Figure 11-22: Clocked Serial Interface Mode Registers 0, 1 (CSIM0, CSIM1) Address Initial...
Page 324: Figure 11-23: Clocked Serial Interface Clock Selection Registers 0, 1 (Csic0, Csic1)
Chapter 11 Serial Interface Function Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). This register can be read/written in 8-bit or 1-bit units. Figure 11-23: Clocked Serial Interface Clock Selection Registers 0, 1 (CSIC0, CSIC1) Address Initial...
Page 325: Figure 11-24: Clocked Serial Interface Reception Buffer Registers 0, 1 (Sirb0, Sirb1)
Chapter 11 Serial Interface Function Clocked serial interface reception buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 326: Figure 11-25: Clocked Serial Interface Reception Buffer Registers L0, L1 (Sirbl0, Sirbl1)
Chapter 11 Serial Interface Function Clocked serial interface reception buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 327: Figure 11-26: Clocked Serial Interface Read-Only Reception Buffer Registers 0, 1 (Sirbe0, Sirbe1)
Chapter 11 Serial Interface Function Clocked serial interface read-only reception buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 328: Figure 11-27: Clocked Serial Interface Read-Only Reception Buffer Registers L0, L1(Sirbel0, Sirbel1)
Chapter 11 Serial Interface Function Clocked serial interface read-only reception buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 329: Figure 11-28: Clocked Serial Interface Transmission Buffer Registers 0, 1 (Sotb0, Sotb1)
Chapter 11 Serial Interface Function Clocked serial interface transmission buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 330: Figure 11-29: Clocked Serial Interface Transmission Buffer Registers L0, L1 (Sotbl0, Sotbl1)
Chapter 11 Serial Interface Function Clocked serial interface transmission buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 331: Figure 11-30: Clocked Serial Interface Initial Transmission Buffer Registers 0, 1 (Sotbf0, Sotbf1)
Chapter 11 Serial Interface Function Clocked serial interface initial transmission buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 332: Figure 11-31: Clocked Serial Interface Initial Transmission Buffer Registers L0, L1 (Sotbfl0, Sotbfl1)
Chapter 11 Serial Interface Function (10) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit units.
Page 333: Figure 11-32: Serial I/O Shift Registers 0, 1 (Sio0, Sio1)
Chapter 11 Serial Interface Function (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 334: Figure 11-33: Serial I/O Shift Registers L0, L1 (Siol0, Siol1)
Chapter 11 Serial Interface Function (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit units.
Page 335: Operation
Chapter 11 Serial Interface Function 11.3.4 Operation Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMD bit of CSIMn register = 0), transfer is started by reading receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). In the transmission/reception mode (TRMD bit of CSIMn register = 1), transfer is started by Note 2 writing to the transmit data buffer register (SOTBn/SOTBLn).
Page 336 Chapter 11 Serial Interface Function Figure 11-34: Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (input/output) (55H)
Page 337: Figure 11-35: Timing Chart According To Clock Phase Selection (1/2)
Chapter 11 Serial Interface Function (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following condi- tions.
Page 338 Chapter 11 Serial Interface Function Figure 11-35: Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (input/output) SIn (input) DO6 DO5 DO4 DO3 DO2 DO1 SOn (output) Reg_R/W INTCSIn interrupt CSOT bit (d) When CKP bit = 1, DAP bit = 1 SCKn (input/output)
Page 339: Figure 11-36: Timing Chart Of Interrupt Request Signal Output In Delay Mode (1/2)
Chapter 11 Serial Interface Function (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSI0n is set (1) upon completion of data transmission/reception. Caution: The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 340 Chapter 11 Serial Interface Function Figure 11-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (input/output) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOT bit Delay Remarks: 1.
Page 341: Figure 11-37: Repeat Transfer (Receive-Only) Timing Chart
Chapter 11 Serial Interface Function Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMD bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 342: Figure 11-38: Repeat Transfer (Transmission/Reception) Timing Chart
Chapter 11 Serial Interface Function (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMD bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3>...
Page 343: Figure 11-39: Timing Chart Of Next Transfer Reservation Period
Chapter 11 Serial Interface Function (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown inFigure 11- Figure 11-39: Timing Chart of Next Transfer Reservation Period (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (input/output) INTCSIn...
Page 344: Figure 11-40: Transfer Request Clear And Register Access Contention
Chapter 11 Serial Interface Function (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 345: Figure 11-41: Interrupt Request And Register Access Contention
Chapter 11 Serial Interface Function - In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 11-41). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 346: Output Pins
Chapter 11 Serial Interface Function 11.3.5 Output pins SCKn pin When the CSIn operation is disabled (CSIE bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). CKS2 CKS1 CKS0 SCKn Pin Output Don’t care Don’t care Don’t care...
Page 347: Dedicated Baud Rate Generators 0, 1 (Brg0, Brg1)
Chapter 11 Serial Interface Function 11.3.6 Dedicated baud rate generators 0, 1 (BRG0, BRG1) Selecting the baud rate generator The CSI0 and CSI1 serial clocks can be selected between dedicated baud rate generator output or internal system clock ( The serial clock source is specified by bits CKS2 to CKS0 of registers CSIC0 and CSIC1 (refer to (2)Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1)).
Page 348: Figure 11-43: Prescaler Mode Registers 0, 1 (Prsm0, Prsm1)
Chapter 11 Serial Interface Function Configuration BRGn is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register n (PRSMn) that controls baud rate signal generation, a prescaler compare register n (PRSCMn) that sets the value of the 8-bit timer counter, and a prescaler (n = 0, 1). (a) Input clock The internal system clock (f ) is input to BRGn.
Page 349: Figure 11-44: Prescaler Compare Registers 0, 1 (Prscm0, Prscm1)
Chapter 11 Serial Interface Function (c) Prescaler compare registers 0, 1 (PRSCM0, PRSCM1) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit or 1-bit units (n = 0, 1). Figure 11-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) Address Initial...
Page 350: Table 11-6: Baud Rate Generator Setting Data
Chapter 11 Serial Interface Function (e) Baud rate setting example Table 11-6: Baud Rate Generator Setting Data <1> When f = 16 MHz BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 <2>...
Page 351: Chapter 12 Fcan Interface Function
Chapter 12 FCAN Interface Function 12.1 Features • Active support of extended format (ISO 11898, former CAN specification version 2.0B active), sup- porting transmission and reception of standard and extended frame format messages • 1 CAN module: • CAN bus speed up to 1 Mbit per second •...
Page 352: Outline Of The Fcan System
Chapter 12 FCAN Interface Function 12.2 Outline of the FCAN System 12.2.1 General The FCAN (Full-CAN) system of the V850E/ VANStorm supports one independent CAN module, which provides an interface to a Controller Area Network (CAN). The CAN module is conform to ISO 11898 part 1-4, former CAN specification version 2.0B active. An external bus transceiver has to be used to connect the CAN module to the CAN bus.
Page 353: Can Memory And Register Layout
Chapter 12 FCAN Interface Function 12.2.2 CAN memory and register layout All buffers and registers of the FCAN system are arranged within a memory layout of 3 KB. Figure 12-2: Memory Area of the FCAN System Address Offset 87FH CAN1 temporary buffer 860H 85FH CAN module section...
Page 354: Table 12-1: Configuration Of The Can Message Buffer Section
Chapter 12 FCAN Interface Function CAN message buffer section The message buffer section consists of 64 message buffers. Each message buffer allocates 32 bytes. The message buffers are not statically distributed and linked to the CAN modules, rather the user must determine the link of a message buffer to a CAN module by software.
Page 355: Table 12-2: Can Message Buffer Registers Layout
Chapter 12 FCAN Interface Function Table 12-2: CAN Message Buffer Registers Layout Access Type Ref. Address Offset Note 1 Name Symbol Page Note 1, 2 1 bit 8 bit 16 bits (m × 20H) + 000H – Reserved – – (m ×...
Page 356: Table 12-3: Relative Addresses Of Can Interrupt Pending Registers
Chapter 12 FCAN Interface Function CAN Interrupt Pending Registers Section The layout of the interrupt pending register section is shown in Table 12-3. Table 12-3: Relative Addresses of CAN Interrupt Pending Registers Address Access Type Ref. Note Offset Symbol Name Comment Page R/W 1 bit 8 bits 16 bits...
Page 357: Table 12-4: Relative Addresses Of Can Common Registers
Chapter 12 FCAN Interface Function CAN Common Registers Section The layout of the common register section is shown in Table 12-4. Table 12-4: Relative Addresses of CAN Common Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits 16 bits ×...
Page 358: Table 12-5: Relative Addresses Of Can Module 1 Registers
Chapter 12 FCAN Interface Function CAN Module Registers Section The appropriate register section of each CAN module is shown in Table 12-5 for CAN module 1. Table 12-5: Relative Addresses of CAN Module 1 Registers Access Type Address Ref. Symbol Name Comment Note...
Page 359: Clock Structure
Chapter 12 FCAN Interface Function 12.2.3 Clock structure All functional blocks within the FCAN system are supplied by a unique clock (f ) derived from the internal system clock (f ) or an external clock (f Figure 12-3: Clock Structure of the FCAN System Time System General Time System...
Page 360: Interrupt Handling
Chapter 12 FCAN Interface Function 12.2.4 Interrupt handling The very high number of interrupt events generated by the FCAN system does not allow to assign an independent interrupt vector of the V850E/ VANStorm to each event. Therefore, the interrupt request signals are bundled into groups and the grouped interrupt request signal is then assigned to an inde- pendent interrupt vector.
Page 361: Time Stamp
Chapter 12 FCAN Interface Function 12.2.5 Time stamp The FCAN system offers a time stamp capture capability at message reception and transmission. The time stamp capture function is used to realize a synchronized, global clock in a CAN network, also called global time system.
Page 362: Figure 12-6: Time Stamp Capturing At Message Transmission
Chapter 12 FCAN Interface Function For the time stamp capturing at message transmission the SOF signal of the transmit message is used as the event trigger (see Figure 12-6). The captured value from the CGTSC counter is written into particular data bytes of the transmit mes- sage’s data field.
Page 363: Message Handling
Chapter 12 FCAN Interface Function 12.2.6 Message handling In the FCAN system the assignment of message buffers to the CAN module is not defined by hardware. Each message buffer in the message buffer section can be assigned to the CAN module by software. The message buffers have individual configuration registers to assign the CAN module and to specify the message buffer type.
Page 364: Table 12-7: Example For Automatic Transmission Priority Detection
Chapter 12 FCAN Interface Function Table 12-7: Example for Automatic Transmission Priority Detection Message Buffer Message Buffer Message Buffer Message Buffer Waiting for Identifier Note1 Number Link Note2 Transmission Address Offset Type 7E0H · · · · · · 300H 2E0H 2C0H CAN 1...
Page 365: Table 12-8: Example For Transmit Buffer Allocation When More Than 5 Buffers Linked To A Can Module
Chapter 12 FCAN Interface Function Table 12-8: Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to a CAN Module Message Buffer Message Buffer Message Buffer Message Buffer Identifier Note1 Number Link Note2 Address Offset Type 7E0H · ·...
Page 366: Table 12-9: Storage Priority For Reception Of Data Frames
Chapter 12 FCAN Interface Function Message reception Due to the vast initialisation possibilities for each message buffer in the FCAN system, it is possible that a received message fits in several message buffers assigned to the CAN module. A fixed rule according to the priority classes has been implemented to avoid arbitrary message stor- age and uncontrolled behaviour.
Page 367: Table 12-11: Inner Storage Priority Within A Priority Class
Chapter 12 FCAN Interface Function Table 12-11: Inner Storage Priority Within a Priority Class Priority First Criteria Priority Second Criteria 1 (high) lowest physical message buffer number 1 (high) DN flag not set 2 (low) next physical message buffer number 1 (high) lowest physical message buffer number 2 (low)
Page 368: Mask Handling
Chapter 12 FCAN Interface Function 12.2.7 Mask handling The FCAN system supports two concepts of message reception, the BasicCAN concept and the Full- CAN concept. In the Full-CAN concept a particular message buffer accepts only one single message, hence there is no further sorting and filtering required by software.
Page 369: Remote Frame Handling
Chapter 12 FCAN Interface Function 12.2.8 Remote frame handling The FCAN macro offers enhanced features for generating remote frames and for the reaction of the CAN module upon remote frames. Generation of a remote frame According to the CAN specification a remote frame has the same format as a data frame except the RTR bit of the control field, which has recessive level, and the data field, which is omitted com- pletely.
Page 370 Chapter 12 FCAN Interface Function Reception of a remote frame The FCAN allows the reception of remote frames in message buffers defined for reception or for transmission. (a) Reception in a receive message buffer If a remote frame is received in a message buffer m (m = 00 to 63) configured for reception, the fol- lowing message buffer information will be updated: M_DLCm message data length code register...
Page 371: Table 12-12: Remote Frame Handling Upon Reception Into A Transmit Message Buffer
Chapter 12 FCAN Interface Function Table 12-12: Remote Frame Handling upon Reception into a Transmit Message Buffer M_CTRLm setting Resulting Automatic Remote Frame Handling RMDE0 RMDE1 DN flag other actions no change – („ignore remote frame“) Clear when transmit message buffer send transmit message buffer (data sent successfully frame) as an automatic answer.
Page 372: Control And Data Registers
Chapter 12 FCAN Interface Function 12.3 Control and Data Registers 12.3.1 Bit set/clear function Direct writing of data (bit operations, read-modify write, direct writing of a target value) is not allowed to few specific registers, where bit setting and bit clearing might be performed by CPU and by the FCAN system.
Page 373: Figure 12-7: 16-Bit Data Write Operation For Specific Registers
Chapter 12 FCAN Interface Function Figure 12-7: 16-Bit Data Write Operation for Specific Registers ST_7 ST_6 ST_5 ST_4 ST_3 ST_2 ST_1 ST_0 CL_7 CL_6 CL_5 CL_4 CL_3 CL_2 CL_1 CL_0 Bit Name Function ST_n Sets the register bit n. 0: No change of register bit n 1: Register bit n is set (1) CL_n Clears the register bit n.
Page 374: Common Registers
Chapter 12 FCAN Interface Function 12.3.2 Common registers CAN stop register (CSTOP) The CSTOP register controls the clock supply of the FCAN system. This register can be read/written in 8-bit and16-bit units. Figure 12-8: CAN Stop Register (CSTOP) Address Initial Note1 value Offset...
Page 375: Figure 12-9: Can Main Clock Select Register (Cgsc) (1/2)
Chapter 12 FCAN Interface Function CAN main clock select register (CGCS) The CGCS register controls the internal memory access clock (f ), which is used as main clock for each CAN module, as well as the global time system clock (f ), used for the time stamp func- tion.
Page 376: Figure 12-10: Configuration Of Fcan System Main Clock
Chapter 12 FCAN Interface Function Figure 12-9: CAN Main Clock Select Register (CGSC) (2/2) Bit Position Bit Name Function 3 to 0 MCP3 to Specifies the prescaler for the memory access clock (f ) (ref. to Fig. 12-10). MCP0 Memory Clock Prescaler MCP3 MCP2...
Page 377: Figure 12-12: Can Global Status Register (Cgst) (1/2)
Chapter 12 FCAN Interface Function CAN global status register (CGST) The CGST register indicates and controls the operation modes of the FCAN system. Additionally the version number of the FCAN system can be obtained. This register can be read in 1-bit, 8-bit and 16-bit units. It can be written in 16-bit units only. For set- ting and clearing certain bits a special set/clear method applies.
Page 378 Chapter 12 FCAN Interface Function Figure 12-12: CAN Global Status Register (CGST) (2/2) Read (2/2) Bit Position Bit Name Function Indicates the global operating mode. 0: Access to CAN module registers is prohibited, except mask registers and Note 1 temporary buffers. 1: Operation of the CAN modules enabled.
Page 379: Figure 12-13: Can Global Interrupt Enable Register (Cgie)
Chapter 12 FCAN Interface Function CAN global interrupt enable register (CGIE) The CGIE register enables the global interrupts of the FCAN system. This register can be read in 1-bit, 8-bit and16-bit units. It can be written in 16-bit units only. For set- ting and clearing certain bits a special set/clear method applies.
Page 380: Figure 12-14: Can Global Time System Counter (Cgtsc)
Chapter 12 FCAN Interface Function CAN global time system counter (CGTSC) The CGTSC register holds the value of the free-running 16-bit CAN global time system counter. (For details refer to Chapters 12.2.3 Clock structure and 12.2.5 Time stamp.) Note 1 This register can be read and written in 16-bit units only.
Page 381: Figure 12-15: Can Message Search Start Register (Cgmss)
Chapter 12 FCAN Interface Function CAN message search start register (CGMSS) The CGMSS register controls the start of a message search. It can be used for a fast message retrieval within the message buffers matching a search criteria (e.g. messages with DN flag set). This register is write-only and must be written in 16-bit units.
Page 382: Figure 12-16: Can Message Search Start Register (Cgmss)
Chapter 12 FCAN Interface Function CAN message search result register (CGMSR) The CGMSR register returns the result of a message search, started by writing the CGMSS regis- ter. This register is read-only and can be read in 1-bit, 8-bit and 16-bit units. Figure 12-16: CAN Message Search Start Register (CGMSS) Address Initial...
Page 383: Can Interrupt Pending Registers
Chapter 12 FCAN Interface Function 12.3.3 CAN interrupt pending registers CAN interrupt pending register (CCINTP) The CCINTP register summarizes all grouped interrupt pending signals. Each of them is assigned to an unambiguous interrupt vector of the V850E/ VANStorm. This register is read-only and can be read in 8-bit and16-bit units. Figure 12-17: CAN Interrupt Pending Register (CCINTP) Address Initial...
Page 384: Figure 12-18: Can Global Interrupt Pending Register (Cgintp) (1/2)
Chapter 12 FCAN Interface Function CAN global interrupt pending register (CGINTP) The CGINTP register indicates the global interrupt pending signals. The interrupt pending flags can be cleared by writing to the register according to the special bit-clear method. (Refer to Chapter 12.3.1) This register can be read in 8-bit and 16-bit units.
Page 385 Chapter 12 FCAN Interface Function Figure 12-18: CAN Global Interrupt Pending Register (CGINTP) (2/2) Write Bit Position Bit Name Function CL_GINT3 Clears the interrupt pending bit GINT3. 0: No change of GINT3 bit. 1: GINT3 bit is cleared (0). CL_GINT2 Clears the interrupt pending bit GINT2. 0: No change of GINT2 bit.
Page 386: Figure 12-19: Can 1 Interrupt Pending Register (C1Intp) (1/2)
Chapter 12 FCAN Interface Function CAN 1 interrupt pending register (C1INTP) The C1INTP register indicates the corresponding CAN module interrupt pending signals. The inter- rupt pending flags can be cleared by writing to the register according to the special bit-clear method.
Page 387 Chapter 12 FCAN Interface Function Figure 12-19: CAN 1 Interrupt Pending Register (C1INTP) (2/2) Write Bit Position Bit Name Function CL_C1INT6 Clears the interrupt pending bit C1INT6. 0: No change of C1INT6 bit. 1: C1INT6 bit is cleared (0). CL_C1INT5 Clears the interrupt pending bit C1INT5. 0: No change of C1INT5 bit.
Page 388: Can Message Buffer Registers
Chapter 12 FCAN Interface Function 12.3.4 CAN message buffer registers Message identifier registers L00 to L63 and H00 to H63 (M_IDL00 to M_IDL63, M_IDH00 to M_IDH63) The M_IDLm, M_IDHm registers specify the identifier and format of the corresponding message m (m = 00 to 63).
Page 389: Figure 12-21: Message Configuration Registers 00 To 63 (M_Conf00 To M_Conf63)
Chapter 12 FCAN Interface Function Message configuration registers 00 to 63 (M_CONF00 to M_CONF63) The M_CONFm registers specify the message type, mask link and CAN module assignment of the corresponding message m (m = 00 to 63). These registers can be read/written 8-bit units. Figure 12-21: Message Configuration Registers 00 to 63 (M_CONF00 to M_CONF63) Address Note 1...
Page 390: Figure 12-22: Message Status Registers 00 To 63 (M_Stat00 To M_Stat63)
Chapter 12 FCAN Interface Function Message status registers 00 to 63 (M_STAT00 to M_STAT63) The M_STATm registers indicate transmit and receive status of the corresponding message m (m = 00 to 63). Bits can be set/cleared only by means of the SC_STATm register. These registers can be read-only in 8-bit units.
Page 391: Table 12-13: Can Message Processing By Trq And Rdy Bits
Chapter 12 FCAN Interface Function Processing of a transmit or receive message by TRQ and RDY flags is summarized in Table 12-13. Table 12-13: CAN Message Processing by TRQ and RDY Bits Message Type Message Processing × Message buffer is disabled for any processing by the assigned CAN module.
Page 392: Figure 12-23: Message Set/Clear Status Registers 00 To 63 (Sc_Stat00 To Sc_Stat63)
Chapter 12 FCAN Interface Function Message set/clear status registers 00 to 63 (SC_STAT0 to SC_STAT63) The SC_STATm registers set/clear the flags of the corresponding M_STATm registers (m = 00 to 63). By means of this register transmission can be requested and reception can be confirmed. These registers can be written-only in 16-bit units.
Page 393: Figure 12-24: Message Data Registers M0 To M7 (M_Datam0 To M_Datam7)
Chapter 12 FCAN Interface Function Message data registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 63) The MDATAm0 to M_DATA7 registers are used to hold the receive or transmit data of the corre- sponding message m (m = 00 to 63). These registers can be read/written in 8-bit units.
Page 394 Chapter 12 FCAN Interface Function Figure 12-24: Message Data Registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 63) (2/2) Bit Position Bit Name Function 7 to 0 D0_7 to Contents of the message data byte 0. (first message data byte) (M_DATAm0) D0_0 7 to 0...
Page 395: Figure 12-25: Message Data Length Code Registers 00 To 63 (M_Dlc00 To M_Dlc63)
Chapter 12 FCAN Interface Function Message data length code registers 00 to 63 (M_DLC0 to M_DLC63) The M_DLCm registers specify the data length code (DLC) of the corresponding message m (m = 00 to 63). The DLC determines how many data bytes have to be transmitted, or received respectively, for the corresponding data frame.
Page 396: Figure 12-26: Message Control Registers 00 To 63 (M_Ctrl00 To M_Ctrl63) (1/2)
Chapter 12 FCAN Interface Function Message control registers 00 to 63 (M_CTRL0 to M_CTRL63) The M_CTRLm registers control the behaviour on reception or transmission of the corresponding message buffer m (m = 00 to 63). These registers can be read/written in 8-bit units. Figure 12-26: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (1/2) Address Note...
Page 397 Chapter 12 FCAN Interface Function Figure 12-26: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (2/2) Bit Position Bit Name Function Enables message buffer m related interrupts. 0: Interrupts related to message buffer m disabled. 1: Interrupts related to message buffer m enabled. Remark: If the message related interrupt is enabled, an interrupt is generated for any of the following conditions:...
Page 398: Figure 12-27: Message Time Stamp Registers 00 To 63 (M_Time00 To M_Time63)
Chapter 12 FCAN Interface Function Message time stamp registers 00 to 63 (M_TIME00 to M_TIME63) The M_TIMEm registers store the captured time stamp value on reception of the corresponding message m (m = 00 to 63). These registers can be read/written in 16-bit units. Figure 12-27: Message Time Stamp Registers 00 to 63 (M_TIME00 to M_TIME63) Address Initial...
Page 399: Can Module Registers
Chapter 12 FCAN Interface Function 12.3.5 CAN Module Registers CAN 1 mask 0 to 3 registers L, H (C1MASKL0 to C1MASKL3, C1MASKH0 to C1MASKH3) The C1MASKL0 to C1MASKL3, and C1MASKH0 to C1MASKH3 registers specify the four accept- ance masks for the CAN module. (For more details refer to Chapter 12.2.7 Mask handling.) These registers can be read/written in 8-bit and 16-bit units.
Page 400: Table 12-14: Address Offsets Of The Can 1 Mask Registers
Chapter 12 FCAN Interface Function Table 12-14: Address Offsets of the CAN 1 Mask Registers Symbol Address Offset C1MASKL0 840H C1MASKH0 842H C1MASKL1 844H C1MASKH1 846H C1MASKL2 848H C1MASKH2 84AH C1MASKL3 84CH C1MASKH3 84EH Note: The register address is calculated according to the following formula: effective address = PP_BASE + address offset Preliminary User’s Manual U14879EE1V0UM00...
Page 401: Figure 12-29: Can 1 Control Register (C1Ctrl) (1/4)
Chapter 12 FCAN Interface Function CAN 1 control register (C1CTRL) The C1CTRL register controls the operating modes and indicates the operating status of the CAN module. This register can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies (refer to Chapter 12.3.1).
Page 402 Chapter 12 FCAN Interface Function Figure 12-29: CAN 1 Control Register (C1CTRL) (2/4) Read (2/3) BOFF Indicates a bus-off status of the CAN module. 0: CAN module is not in bus-off state (transmission error counter < 256) 1: CAN module is in bus-off state (transmission error counter = 256) TSTAT Indicates the transmission status.
Page 403 Chapter 12 FCAN Interface Function Figure 12-29: CAN 1 Control Register (C1CTRL) (3/4) Read (3/3) STOP Selects the CAN stop mode. 0: CAN module is not stop mode. 1: CAN module stop mode selected. Remarks: 1. The CAN stop mode can be entered only if the CAN module is already in sleep mode (SLEEP = 1).
Page 404 Chapter 12 FCAN Interface Function Figure 12-29: CAN 1 Control Register (C1CTRL) (4/4) Write (2/2) Bit Position Bit Name Function 13, 5 ST_DLEVT, Sets/clears the DLEVT bit. CL_DLEVT ST_DLEVT CL_DLEVT Status of DLEVT bit DLEVT bit is cleared (0). DLEVT bit is set (1). Others No change in DLEVT bit value.
Page 405: Figure 12-30: Can 1 Definition Register (C1Def) (1/3)
Chapter 12 FCAN Interface Function CAN 1 definition register (C1DEF) The C1DEF register defines normal and diagnostic operation and indicates CAN bus error and states of the CAN module. This register can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies (refer to Chapter 12.3.1).
Page 406 Chapter 12 FCAN Interface Function Figure 12-30: CAN 1 Definition Register (C1DEF) (2/3) Read (2/2) Bit Position Bit Name Function SSHT Defines the single-shot mode for the CAN module. 0: Normal operating mode 1: Single-shot mode Remarks: 1. In single shot mode the CAN module tries to transmit a message only once, and the TRQ flag of the corresponding message is cleared regardless whether the transmission was successful (no error occurred), or not.
Page 407 Chapter 12 FCAN Interface Function Figure 12-30: CAN 1 Definition Register (C1DEF) (3/3) Write Bit Position Bit Name Function 15, 7 ST_DGM, Sets/clears the DGM bit. CL_DGM ST_DGM CL_DGM Status of DGM bit DGM bit is cleared (0). DGM bit is set (1). Others No change in DGM bit value.
Page 408: Figure 12-31: Can 1 Information Register (C1Last)
Chapter 12 FCAN Interface Function CAN 1 information register (C1LAST) The C1LAST register returns the number of the last received message and last CAN protocol error of the CAN module. This register can be read-only in 8-bit and 16-bit units. Figure 12-31: CAN 1 Information Register (C1LAST) Address Initial...
Page 409: Figure 12-32: Can 1 Error Counter Register (C1Erc)
Chapter 12 FCAN Interface Function CAN 1 error counter register (C1ERC) The C1ERC register reflects the status of the transmit and the receive error counters of the CAN module. This register can be read-only in 8-bit and 16-bit units. Figure 12-32: CAN 1 Error Counter Register (C1ERC) Address Initial value...
Page 410: Figure 12-33: Can 1 Interrupt Enable Register (C1Ie) (1/3)
Chapter 12 FCAN Interface Function CAN 1 interrupt enable register (C1IE) The C1IE register enables the transmit, receive and error interrupts of the CAN module. This register can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies (refer to Chapter 12.3.1).
Page 411 Chapter 12 FCAN Interface Function Figure 12-33: CAN 1 Interrupt Enable Register (C1IE)(2/3) Write Bit Position Bit Name Function 14, 6 ST_E_INT6, Sets/clears the E_INT6 bit. CL_E_INT6 ST_E_INT6 CL_E_INT6 Status of E_INT6 bit E_INT6 bit is cleared (0). E_INT6 bit is set (1). Others No change in E_INT6 bit value.
Page 412 Chapter 12 FCAN Interface Function Figure 12-33: CAN 1 Interrupt Enable Register (C1IE)(3/3) Write Bit Position Bit Name Function 8, 0 ST_E_INT0, Sets/clears the E_INT0 bit. CL_E_INT0 ST_E_INT0 CL_E_INT0 Status of E_INT0 bit E_INT0 bit is cleared (0). E_INT0 bit is set (1). Others No change in E_INT0 bit value.
Page 413: Figure 12-34: Can 1 Bus Activity Register (C1Ba) (1/2)
Chapter 12 FCAN Interface Function CAN 1 bus activity register (C1BA) The C1BA register indicates the status of the CAN bus activities of the CAN module. This register can be read-only in 8-bit and 16-bit units. Figure 12-34: CAN 1 Bus Activity Register (C1BA) (1/2) Address Initial Note...
Page 414 Chapter 12 FCAN Interface Function Figure 12-34: CAN 1 Bus Activity Register (C1BA) (2/2) Bit Position Bit Name Function 7 to 0 TMNO7 to Indicates the message buffer, which is either waiting to be transmitted or in transmis- TMNO0 sion progress. TMNO7 to TMNO0 Number of Transmit Message Buffer Current transmit message buffer (waiting for trans-...
Page 415: Figure 12-35: Can 1 Bit Rate Prescaler Register (C1Brp) (1/2)
Chapter 12 FCAN Interface Function CAN 1 bit rate prescaler register (C1BRP) The C1BRP register specifies the bit rate prescaler and CAN bus speed of the CAN module. The register layout depends on the TLM bit (bit 15), and distinguishes between 6-bit prescaler (TLM bit = 0) and 8-bit prescaler (TLM bit = 1).
Page 416 Chapter 12 FCAN Interface Function Figure 12-35: CAN 1 Bit Rate Prescaler Register (C1BRP) (2/2) Bit Position Bit Name Function 7 to 0 BRP7 to Specifies the bit rate prescaler for the CAN protocol layer. (TLM = 1) BRP0 TLM = 0: (TLM = 1) Bit Rate Prescaler BRP5...
Page 417: Figure 12-36: Can Bus Bit Timing
Chapter 12 FCAN Interface Function CAN 1 synchronization control register (C1SYNC) A bit in a CAN frame is built by a programmable number of time quanta (TQ), as shown in the Fig- ure 12-36 below. Figure 12-36: CAN Bus Bit Timing PROP_SEG PHASE_SEG1 PHASE_SEG2...
Page 418: Figure 12-37: Can 1 Synchronization Control Register (C1Sync) (1/2)
Chapter 12 FCAN Interface Function The C1SYNC register specifies the data bit time (DBT), sampling point position (SPT) and synchro- nisation jump width (SJW) of the CAN module. This register can be read/written in 8-bit and 16-bit units. However, write access is only permitted in initialisation mode (ISTAT bit of the C1CTRL register = 1) Figure 12-37: CAN 1 Synchronization Control Register (C1SYNC) (1/2) Address...
Page 419 Chapter 12 FCAN Interface Function Figure 12-37: CAN 1 Synchronization Control Register (C1SYNC) (2/2) Bit Position Bit Name Function 4 to 0 DBT4 to Specifies the number of TQ per bit. DBT0 Data Bit Time DBT4 DBT3 DBT2 DBT1 DBT0 DBT = (q + 1) TQ Setting prohibited •...
Page 420: Figure 12-38: Can 1 Bus Diagnostic Information Register (C1Dinf)
Chapter 12 FCAN Interface Function (10) CAN 1 bus diagnostic information register (C1DINF) The C1DINF register reflects the last transmission on CAN bus. This register can be read-only in 1-bit, 8-bit and 16-bit units. It is only accessible when diagnostic mode is set (C1DEF register’s MOM bit = 1).
Page 421: Operating Considerations
Chapter 12 FCAN Interface Function 12.4 Operating Considerations 12.4.1 Rules to be observed for correct baudrate settings Observing the following rules for the baud rate setting assures correct operation of a CAN module and compliance to the CAN protocol specification. Rule for sampling point (SPT) setting: The sample point position needs to be programmed between 3 TQ and 17 TQ, which corresponds to the SPT4 to SPT0 bits of the C1SYNC register:...
Page 422: Example For Baudrate Setting Of Can Module
Chapter 12 FCAN Interface Function 12.4.2 Example for baudrate setting of CAN module To illustrate how to calculate the correct setting of the registers C1BRP and C1SYNC the following example is given: Requirements from CAN bus: - FCAN system global frequency f = 16 MHz - CAN bus baud rate f = (83...
Page 423 Chapter 12 FCAN Interface Function TLM=1: BRP7 to BRP0 = 00001011B (11) (prescaler BRP = 12) DBT4 to DBT0 = 01111B (15) (data bit time DBT = 16 TQ) SPT4 to SPT0 = 01100B (12) (sampling point SPT = 13 TQ) BRP7 to BRP0 = 00001111B (15) (prescaler BRP = 16) DBT4 to DBT0 =...
Page 424: Ensuring Data Consistency
Chapter 12 FCAN Interface Function 12.4.3 Ensuring data consistency If the CPU reads data from the CAN message buffers, the consistency of data read has to be ensured. Therefore two mechanisms are provided: • Sequential data read • Burst mode data read Sequential data read If the data is read by the CPU by sequential accesses to the CAN message buffers, the following sequence has to be observed:...
Page 425 Chapter 12 FCAN Interface Function Burst Mode Data Read For faster access to a complete message the burst read mode is applicable. In burst read mode the complete message is copied from the internal message buffer to a tempo- rary read buffer located outside the CAN memory section. This allows read access without any wait, if the CAN memory is accessed by the CAN module while the CPU tries to read data.
Page 426: Operating States Of The Can Module
Chapter 12 FCAN Interface Function 12.4.4 Operating states of the CAN module The different operating states and the state transitions of the CAN module are shown in the state transition diagram in Figure 12-40. Figure 12-40: State Transition Diagram for the CAN Module Initialisation Mode INIT = 0 CxCTRL[ ISTAT ] =1...
Page 427: Initialization Routines
Chapter 12 FCAN Interface Function 12.4.5 Initialization routines Below the necessary steps for correct start-up of the CAN interface are explained. Caution: It is very important that the software programmer observes the sequence given in the following paragraphs. Otherwise unexpected operation of the CAN interface or any CAN module can occur.
Page 428 Chapter 12 FCAN Interface Function Example for C routine: int CAN_GlobalInit (void) unsigned char i; CGST = 0x00FF; // clear all flags of CGST CGIE = 0x00FF; // disable global interrupts CGCS = 0x0000; // define internal clock CGTSC = 0x0000; // clear CAN global time system counter CGTEN = 0x0000;...
Page 429: Figure 12-42: Initialization Sequence For The Can Module
Chapter 12 FCAN Interface Function Initialization sequence for the CAN Module The CAN module must be initialized by the sequence according to Figure 12-42. Figure 12-42: Initialization Sequence for the CAN module INIT CAN MODULE Init the module registers: - CxCTRL (but do not clear the INIT flag) - CxDEF - CxIE...
Page 430 Chapter 12 FCAN Interface Function Example for C routine: int CAN_ModuleInit (unsigned char module_no, unsigned short brp_value, unsigned short sync_value) can_module_type *can_mod_ptr; // define ptr can_mod_ptr = &can_module[module_no]; // load ptr can_mod_ptr->CxCTRL = 0x00FE; // clear CxCTRL // except INIT can_mod_ptr->CxDEF = 0x00FF;...
Page 431: Figure 12-43: Setting Can Module Into Initialization State
Chapter 12 FCAN Interface Function Setting the CAN Module into initialization state The following routine is required if the CAN module has to be set from normal operation into initiali- sation mode. Please notice that the CAN module are automatically set to initialisation mode after reset. Therefore the sequence is only required if the CAN module is already in normal operation.
Page 432 Chapter 12 FCAN Interface Function Shutdown of the FCAN system If the clock to the CAN interface should be switched off for power saving, the following sequence has to be executed for correct termination of any CAN bus activity: <1> For the CAN module <a>...
Page 433: Chapter 13 Full Van (Fvan)
VAN protocol in the DATA LINK LAYER and the top level of the PHYSICAL layer of the OSI communication model. The NEC FVAN Controller handles the transmission and the reception of VAN frames, as well as pro- viding error management and diagnostic functionality.
Page 434: Features
Chapter 13 Full VAN (FVAN) 13.1.2 Features • Fully compliant to VAN specification ISO/11519-3. • Handles all specified module types. • Handles all specified message types. • Handles retransmission of frames on contention and errors. • 3 separate line inputs with automatic diagnosis and selection. •...
Page 435: Block Diagram
Chapter 13 Full VAN (FVAN) 13.1.3 Block Diagram Figure 13-1: Block Diagram INTFVANn Micro interface Address bus Status and control registers Data bus Control bus Source Status bus Protocol controller 128 bytes diagnosis and state machine and selection logic ID registers Message Reception buffer RAM...
Page 436: Operation Of Fvan
Chapter 13 Full VAN (FVAN) 13.2 Operation of FVAN 13.2.1 Interrupt If an event occurs in the FVAN, that needs the attention of the processor, this will be signalled with an interruption. If all flags in the interrupt status register are set to “0” value, the interruption signal is inac- tive.
Page 437: Oscillator
Chapter 13 Full VAN (FVAN) 13.2.3 Oscillator The clock generator in the FVAN generates all needed timing signals for the operation of the circuit. The clock generator is controlled by a 4-bit code existing out of the clock divider bits CD2 to CD0 and the divided by 5 bit DIV5 in the line control register LCR.
Page 438: Van Protocol
Chapter 13 Full VAN (FVAN) 13.3 VAN protocol 13.3.1 Line Interface There are three line inputs and one line output available on the FVAN. Which of the three inputs to use is either programmable by software or automatically selected by a diagnosis system. The diagnosis system continuously monitors the data received through the three inputs, and compares each of them with the selected line.
Page 439: Van Frame
If the module is the receiver, the RAK bit read on the VAN bus is written to in the reception buffer. Note that the NEC VAN Controller allows the Request of acknowledge for any kind of services. R/W: Read/Write access...
Page 440: Figure 13-4: Unacknowledged Data Transfer
Chapter 13 Full VAN (FVAN) The MAC Services The MAC services described in the VAN protocol are split into four types: (a) Unacknowledged data transfer This transfer type allows the transfer of data between modules without acknowledge. Figure 13-4: Unacknowledged data transfer Sending C O M Module...
Page 441: Figure 13-6: Reply Request Message With Immediate Response Frame With Acknowledges
Chapter 13 Full VAN (FVAN) (c) Remote transmission with immediate reply In this message type, the answer is provided in the same frame as the request. Figure 13-6: Reply Request Message with immediate response frame with acknowledges Sending C O M Module Identifier Requested...
Page 442: Figure 13-7: Request Reply Answer Without In Frame Response With Acknowledgment
Chapter 13 Full VAN (FVAN) (d) Remote transmission with deferred reply The remote transmission occurred when a remote transfer was requested and the requested mod- ule is not able to answer inside the frame. Figure 13-7: Request Reply answer without in frame response with acknowledgment Sending C O M Module...
Page 443 Chapter 13 Full VAN (FVAN) VAN operation description The IFS (inter frame space) is defined to be a minimum of 4 Time Slots. The FVAN, accepts an IFS of zero Time slot for the reception. Once the bus has been determined as being free, the module can now, if it is an autonomous mod- ule, initiate a frame or, if it is a synchronous access module, wait until it detects a SOF sequence.
Page 444: Diagnosis System
Chapter 13 Full VAN (FVAN) 13.3.3 Diagnosis System Caution: The purpose of the diagnosis system is to detect any short or open circuits on either of the bus signal lines DATA or DATAB and to permit, if it is possible, to carry the communications on the non-defective line.
Page 445: Figure 13-9: Diagnosis States
Chapter 13 Full VAN (FVAN) Diagnosis States If the diagnosis system finds a failure on either of the VAN bus signals, it changes from nominal to degraded mode, and connects the line receiver not coupled with the failing signal to the reception logic.
Page 446: Table 13-3: Status Bits: Sa & Sb
Chapter 13 Full VAN (FVAN) Table 13-3: Status bits: Sa & Sb Communication Mode nominal Fault no fault on VAN bus Status differential communication on DATA and DATA Mode degraded on DATA Fault fault on DATA Status communication on DATA Mode degraded on DATA Fault...
Page 447 Chapter 13 Full VAN (FVAN) Internal Operations (a) Digital Filtering If several spurious pulses occur during one bit, the diagnosis for defective conductor may be cor- rupted. To avoid such errors, digital filters are implemented. Filtering operation is based on sam- pling of the comparator output signals.
Page 448: Generation Of Internal Signals
Chapter 13 Full VAN (FVAN) 13.3.4 Generation of Internal Signals RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see Chapters 13.3.3 "Diagnosis System" and 13.3.5 "Programming Modes"). The RI signal is disabled in automatic selection mode. The RI signal is a pulse generated when an EOF is detected.
Page 449: Registers Description
Chapter 13 Full VAN (FVAN) 13.4 Registers Description 13.4.1 Memory Map All control registers and message data bytes of the FVANs are located in the programmable peripheral area. The FVANs can be accesses through its programmable peripheral area only. The base address of this programmable peripheral area can be determined by programming the BPC register (see Chapter 3.4.9 “Programmable peripheral I/O registers”...
Page 450: Table 13-6: Memory Map Fvan Macro
Chapter 13 Full VAN (FVAN) Table 13-6: Memory Map FVAN macro Address Registers Address Messages 0x78 to 0x7F (R/W) Channel 13 0xFF Data Byte 127 0x70 to 0x77 (R/W) Channel 12 0x68 to 0x6F (R/W) Channel 11 0x60 to 0x67 (R/W) Channel 10 0x58 to 0x5F (R/W) Channel 9...
Page 451: Control And Status Registers
Chapter 13 Full VAN (FVAN) 13.4.2 Control and Status Registers Line Control Register Address R/W After Reset DIV5 IVTX IVRX xxxn100 Note Remark: Bits 2 and 3 must always be written to logical zero “0”. Address R/W After Reset DIV5 IVTX IVRX xxxn100...
Page 452: Table 13-7: Retries
Chapter 13 Full VAN (FVAN) Transmit Control Register Address R/W After Reset VER2 VER1 VER0 xxxn100 Note Address R/W After Reset VER2 VER1 VER0 xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 453 Chapter 13 Full VAN (FVAN) Diagnosis Control Register Address R/W After Reset SDC3 SDC2 SDC1 SDC0 ETIP ESDC xxxn100 Note Address R/W After Reset SDC3 SDC2 SDC1 SDC0 ETIP ESDC xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 454: Table 13-8: System Diagnosis Clock Divider
Chapter 13 Full VAN (FVAN) Bit Position Bit Name Function 4 to 7 SDC0 to SDC divider SDC3 The time slot clock (TSCLK) is used to generate the SDC clock. TSCLK / SDC Divider = SDC clock.n. Table 13-8: System Diagnosis Clock Divider SDC DIVIDER (3:0) Divide by 0000...
Page 455 Chapter 13 Full VAN (FVAN) Command Register Address R/W After Reset GRES SLEEP IDLE ACTI REAR MDSC xxxn100 Note Address R/W After Reset GRES SLEEP IDLE ACTI REAR MDSC xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 456 Chapter 13 Full VAN (FVAN) Bit Position Bit Name Function GRES General Reset The reset is active when the bit GRES = 1 but the user has to set the GRES to 0 to desactivate the reset. The soft reset is like an external reset 0: Reset inactive 1: Reset active Caution: Before using FVANn (n=0, 1) do a soft reset to initialize the...
Page 457: Table 13-10: Diagnosis System Status Bits
Chapter 13 Full VAN (FVAN) Line Status Register Address R/W After Reset xxxn100 Note Address R/W After Reset xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map” on page 449 and 3.4.9 “Programmable peripheral I/O registers” on page 80) This register reports the operation mode of the FVAN in the Sleep an Idle bits (Command Register located at address 0×03) as well as the diagnosis system status bits Sa to Sc discussed in Chapter 13.3.3 "Diagnosis System".
Page 458 Chapter 13 Full VAN (FVAN) Transmission Status Register Address R/W After Reset NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0 xxxn100 Note Address R/W After Reset NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0 xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 459 Chapter 13 Full VAN (FVAN) Last Message Status Register (0x06) Address R/W After Reset LMSR NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0 xxxn100 Note Address R/W After Reset LMSR NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0 xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 460 Chapter 13 Full VAN (FVAN) Last Error Status Register Address R/W After Reset LESR TERROR ACKE TERROR TERROR xxxn100 Note Address R/W After Reset LESR TERROR ACKE TERROR TERROR xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 461: Figure 13-10: Acke Status Bit
Chapter 13 Full VAN (FVAN) Figure 13-10: ACKE Status bit DLC: Producer RAK = 0 EOD field ACK field ACKE = 0 expected ACKE = 1 received ACKE = 1 received ACKE = 1 received RAK* = 1 RAK*: bit of the frame COMMAND field EOD field ACK field ACKE = 0...
Page 462: Figure 13-11: Fv Status Bit
Chapter 13 Full VAN (FVAN) Figure 13-11: FV Status bit DLC: Consumer EOD field ACK field FV = 0 expected FV = 1 received FV = 1 received FV = 1 received EOD field ACK field FV = 0 expected FV = 1 received received...
Page 463: Figure 13-12: Exceeded Retry With Mr[3..0] = 3
Chapter 13 Full VAN (FVAN) Interrupt Status Register Address R/W After Reset RNOK xxxn100 Note Address R/W After Reset RNOK xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map” on page 449 and 3.4.9 “Programmable peripheral I/O registers” on page 80) RST: Reset interrupt.
Page 464 Chapter 13 Full VAN (FVAN) (10) Interrupt Enable Register Address R/W After Reset TOKE ROKE RNOKE xxxn100 Note Address R/W After Reset TOKE ROKE RNOKE xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 465 Chapter 13 Full VAN (FVAN) (11) Interrupt Reset Register (0x0B) Address R/W After Reset RSTR TOKR ROKR RNOKR xxxn100 Note Address R/W After Reset RSTR TOKR ROKR RNOKR xxxn101 Note Note: xxxn depends on the address setting of A27 to A14 of BPC register (see Chapters 13.4.1 “Memory Map”...
Page 466: Figure 13-13: Update Of The Status Register
Chapter 13 Full VAN (FVAN) Figure 13-13: Update of the Status Register Interrupt Status RNOK Register Internal INTFVANn RESET Flag Flag Flag Flag Flag Write Write Write Write Write Interrupt Enable ROKE RNOKE TOKE Register TOKR ROKR RSTR RNOKR Interrupt Reset Register ID + COM + DATA + CRC PREAMBULE...
Page 467: Channel Registers
Chapter 13 Full VAN (FVAN) 13.4.3 Channel Registers There are a total of 14 channel register sets, each of them occupy 8 bytes. Each set contains two 2x8- bit registers for the identifier tag, identifier mask and command field plus two 1x8-bit registers for DMA pointer and message status.
Page 468 Chapter 13 Full VAN (FVAN) Identifier Tag and Command Registers (ITCR): The identifier tag and command registers are located at the base_address and base_address + 1. They allow the user to specify the full 12-bits identifier field of the ISO standard and the 4-bits com- mand.
Page 469 Chapter 13 Full VAN (FVAN) Message Pointer Register (MPR): The message pointer register at address (base_address + 0x02) is 8 bits wide. It indicates where in the Message DATA RAM area the message buffer is located. Address MESS_ DRAK M_P6 M_P5 M_P4 M_P3...
Page 470 Chapter 13 Full VAN (FVAN) Message Length And Status Register (MLSR): The message length and status register at address (base_address + 0x03) is also 8 bits wide. It indicates the reserved length for the message in the Message DATA RAM area. Address MESS_ M_L4...
Page 471 Chapter 13 Full VAN (FVAN) Identifier Mask Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise mask- ing of the comparison between the identifier received and the identifier specified. Address IMR1 ID_M3 ID_M2 ID_M1 ID_M0 Base_address+07H R/W Address IMR2...
Page 472: Figure 13-14: Message Buffer Structure For Transmission
Chapter 13 Full VAN (FVAN) Mailbox The mailbox contains all the messages received or to be transmitted. Each message is linked to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x080 to 0x0FF for FVAN0 and from 0x180 to 0x1FF for FVAN1 (see Chapter 13.4.1 "Memory Map").
Page 473: Figure 13-15: Message Buffer Structure For Reception
Chapter 13 Full VAN (FVAN) Figure 13-15: Message buffer structure for reception Message Length & Status Register Message Pointer Register M_L [4..0] DRAK M_P [6..0] CHER CHTx CHRx Message 0x80+M_P+n+1 Received DATA n-1 ³ Received DATA 0 0x80+M_P ID[11..0] DATA 0 DATAn-1 Received DATA Frame, immediate or deffered reply Preliminary User’s Manual U14879EE1V0UM00...
Page 474: Figure 13-16: Message Status Updating
Chapter 13 Full VAN (FVAN) Message Status (pointed by: Message Pointer Register) Address R/W MSMPR RRAK RRNW RRTR RM_L4 RM_L3 RM_L2 RM_L1 RM_L0 Remark: Register has no significant value in case of message to be transmitted RRAK: Received RAK bit. This bit is the RAK bit coming from the COM field of the received frame.
Page 475 Chapter 13 Full VAN (FVAN) Message Data (pointed by: Message Pointer Register + 1) DATA0 is the first received (or transmitted) byte, DATAn-1 is the last one. Notes: 1. If the length reserved (in the message length & status register) for an incoming frame is 2 bytes less, the FVAN will write the 2 bytes of the CRC field in the message buffer just after DATAn-1.
Page 476: Functional Description
Chapter 13 Full VAN (FVAN) 13.5 Functional Description 13.5.1 Messages Types There are 5 basic message types defined in the FVAN. Two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames.
Page 477: Table 13-17: Reply Request Message Without Transmission
Chapter 13 Full VAN (FVAN) The second case is that another module on the bus replies with an in-frame reply. In this case the mes- sage type will pass immediately into the after reception state, without passing the after transmission state.
Page 478: Priority Among The Different Channels
Chapter 13 Full VAN (FVAN) Table 13-21: Inactive Message Inactive Message Transmitted Received Recommended Don’t care Don’t care After transmission Don’t care After reception Don’t care Illegal reply request The table above shows all inactive messages types. The last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied.
Page 479: Retries, Rearbitrate And Abort
Chapter 13 Full VAN (FVAN) 13.5.3 Retries, Rearbitrate and Abort Retries and rearbitrate commands are located, respectively, in the Transmit Control Register page 452 and in the Command Register page 455. An abort command is located in each channel register set, in the Message Length &...
Page 480 Chapter 13 Full VAN (FVAN) Retries The purpose of retries feature is to provide, for the user, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame.The maximum of retries is programmable through MR[3:0] of the Trans- mit Control Register page 452.
Page 481: Figure 13-18: Rearbitrate Example
Chapter 13 Full VAN (FVAN) Typical example • Max_retries = 1 (2 transmissions attempts). • If Ch 8 is in a retry loop and the user wants to transmit the Ch 5 without waiting for the end of the loop, the user can use the rearbitrate command. •...
Page 482: Figure 13-19: Idle And Rearbitrate Example
Chapter 13 Full VAN (FVAN) Figure 13-19: Idle and rearbitrate example Retry counter=0 First attempt Xmit Ch8 Activate Ch5 REARBITRATE Ex : FCS Error (not seen by application) Retry counter=0 Xmit Ch5 IDLE Command Set CHTx/Ch5 & IT ROK Retry counter=0 First attempt Xmit Ch8 Ex : FCS Error...
Page 483: Figure 13-20: Disable Channel After Rearbitrate Example
Chapter 13 Full VAN (FVAN) Disable channel after rearbitrate (same example (3)"Typical example"). Figure 13-20: Disable channel after rearbitrate example Retry counter=0 First attempt Xmit Ch8 Activate Ch5 REARBITRATE Disable Ch8 Ex : FCS Error (not seen by application) Retry counter=0 Xmit Ch5 Ex : ACK Error (not seen by application)
Page 484: Figure 13-21: Abort Example
Chapter 13 Full VAN (FVAN) Abort An abort command is dedicated to channels already enabled in transmission. For example, this command can be used to break the retry procedure on one channel. Abort channel is done by set- ting the Error bit (CHER) in the Message Length & Status Register (base_address + 0x02). This command is taken into account if the channel aborted is not transmitted.
Page 485: Activate, Idle And Sleep Modes
Chapter 13 Full VAN (FVAN) 13.5.4 Activate, Idle and Sleep Modes Sleep, idle and activate commands are located in the Command Register page 455. These three com- mands are general commands for the FVAN. Idle and activate commands After reset, the FVAN starts in idle mode. In this mode, the oscillator operates, but the circuit cannot transmit or receive anything on the VAN bus.
Page 486 Chapter 13 Full VAN (FVAN) Sleep command If the user sets the sleep bit (SLEEP), the FVAN enters in sleep mode, whatever are the values of activate and idle bits. The internal oscillator is immediately stopped. Accesses to all registers (and to the messages) are also possible. To exit from this mode the user must apply either an hardware reset (external RESET pin) either an software reset (GRES bit).
Page 487: Linked Channels
Chapter 13 Full VAN (FVAN) 13.5.5 Linked Channels The link feature allows two channels to share the same Message area, the message pointer and the message length assumes this property: • Zero value as message length (M_L [4:0] / base_address + 0x03) declares the channel linked to another channel.
Page 488 [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 489: Chapter 14 A/D Converter
Chapter 14 A/D Converter 14.1 Features • 10-bit resolution on-chip A/D converter • Analog inputs: 12 channels • Separate on-chip A/D conversion result registers for each analog input - 10 bits × 12 registers • A/D conversion trigger modes - A/D trigger mode - A/D trigger polling mode - Timer trigger mode •...
Page 490: Configuration
Chapter 14 A/D Converter 14.2 Configuration The A/D converter,1which employs a successive approximation technique, performs A/D conversion operation using A/D scan mode registers 0 and 11(ADSCM0,1ADSCM1) and A/D conversion result registers ADCRm (m = 0 to 11). Input circuit The input circuit selects an analog input (ANIm) according to the mode set in the ADSCM01register and sends it to the sample and hold circuit (m = 0 to 11).
Page 491 Chapter 14 A/D Converter The AV pin is used to input reference voltage to the A/D converter. A signal input to the ANIm1pin is converted to a digital signal based on the voltage applied between AV and AV Note (m = 0 to 11). If not using the AV pin, connect it to AV or AV Note: When connecting the AV...
Page 492: Figure 14-1: Block Diagram Of A/D Converter
Chapter 14 A/D Converter Figure 14-1: Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 Comparator Sample and and D/A ANI4 hold circuit converter ANI5 ANI11 SAR (10) INTAD ADCR0 Controller ADCR1 INTPE10/TINTCCE10 ADCR2 INTDET ADCR3 ADCR4 ADCR5 ADCR11 ADSCM0 (16) ADSCM1 (16) ADETM (16) Internal bus...
Page 493: Control Registers
Chapter 14 A/D Converter 14.3 Control Registers A/D scan mode register 0 (ADSCM0) The ADSCM0 register is a 16-bit register that selects analog input pins, specifies operation modes, and controls conversion operation. It can be read or written in 1-bit, 8-bit or 16-bit units. However, writing to the ADSCM0 register dur- ing A/D conversion operation interrupts the conversion operation and the data is lost.
Page 494 Chapter 14 A/D Converter Figure 14-2: A/D Scan Mode Register 0 (ADSCM0) (2/2) Bit position Bit name Function 7 to 4 SANI3 to The bits SANI3 to SANI0 specify the analog input pin mode for which the 1st conversion is SANI0 performed in scan mode.
Page 495: Figure 14-3: A/D Scan Mode Register 1 (Adscm1)
Chapter 14 A/D Converter A/D scan mode register 1 (ADSCM1) The ADSCM1 register is a 16-bit register that sets the conversion time of the A/D converter. It can be read or written in 1-bit, 8-bit, or 16-bit units. Figure 14-3: A/D Scan Mode Register 1 (ADSCM1) Address Initial value...
Page 496 Chapter 14 A/D Converter (a) Conversion time setting In order to prevent a drastic change of A/D conversion time even when the oscillation frequency is changed, the conversion speed of a operation stage can be adjusted. By the selection bits FR2 to FR0 in the ADSCM1 register the SAR compare time T can be set in the range of 20/f to 140/f...
Page 497 Chapter 14 A/D Converter (b) Start of conversion trigger setup timing When starting the start of conversion by internal timer interrupt signal (TINTCCE10) an additional setup time T of 8 system clocks has to be considered. TRGAD ⁄ TRGAD Thus the total time of A/D conversion T including the trigger setup time is as follows.
Page 498: Figure 14-4: A/D Voltage Detection Mode Register (Adetm)
Chapter 14 A/D Converter A/D voltage detection mode register (ADETM) The ADETM register is a 16-bit register that sets voltage detection mode. In voltage detection mode a reference voltage value is compared with the analog input pin for which voltage detection is being performed, and an interrupt is set in response to the comparison result.
Page 499: A/D Conversion Result Registers 0 To 11 (Adcr0 To Adcr11)
Chapter 14 A/D Converter A/D conversion result registers 0 to 11 (ADCR0 to ADCR11) The ADCRm registers are 10-bit registers that hold the results of A/D conversions (m = 0 to 11). These registers can only be read in 16-bit units. When reading 10 bits of data of an A/D conversion result from an ADCRm register, only the lower 10 bits are valid and the upper 6 bits always read 0.
Page 500: Figure 14-6: Relationship Between Analog Input Voltages And A/D Conversion Results
Chapter 14 A/D Converter Table 14-2: Correspondence between each Analog Input Pin and ADCRm Registers Analog Input Pin A/D Conversion Result Register ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 ANI8 ADCR8 ANI9 ADCR9 ANI10...
Page 501: Interrupt Requests
Chapter 14 A/D Converter 14.4 Interrupt Requests The A/D converter generates two kinds of interrupts. • A/D conversion termination interrupt (INTAD) • Voltage detection interrupt (INTDET) A/D conversion termination interrupt (INTAD) In A/D conversion enabled status, an A/D conversion termination interrupt is generated when a specified number of A/D conversions have terminated.
Page 502: A/D Converter Operation
Chapter 14 A/D Converter 14.5 A/D Converter Operation 14.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the Note 1 ADSCM0 .
Page 503: Operation Modes And Trigger Modes
Chapter 14 A/D Converter 14.5.2 Operation modes and trigger modes Several conversion operations can be specified for A/D converter1 by specifying operation modes and trigger modes. Operation modes and trigger modes are set using the ADSCM0 register. The relationship between operation modes and trigger modes is shown below. Trigger Mode Operation Mode Setting of ADSCM0...
Page 504: Figure 14-7: Example Of Select Mode Operation Timing (Ani1)
Chapter 14 A/D Converter Operation modes The two operation modes are select mode and scan mode. These modes are set using the ADSCM0 register. (a) Select mode In select mode the A/D converts one analog input specified in the ADSCM0 register. The conver- sion result is stored in the ADCRm register corresponding to the analog input (ANIm) (m = 0 to 11).
Page 505: Figure 14-8: Example Of Scan Mode Operation Timing (4-Channel Scan (Ani0 To Ani3))
Chapter 14 A/D Converter (b) Scan mode The scan mode sequentially selects and converts pin input voltage from the A/D conversion start analog input pin through the A/D conversion termination analog input pin specified in the ADSCM0 register. It stores the A/D conversion result in the ADCRm register corresponding to the analog input (m = 0 to 11).
Page 506: Operation In A/D Trigger Mode
Chapter 14 A/D Converter 14.6 Operation in A/D Trigger Mode Setting the CE bit of the ADSCM0 register to 1 starts A/D conversion immediately. 14.6.1 Operation in select mode One analog input specified in the ADSCM0 register is A/D converted at a time and the result is stored in an ADCRm register.
Page 507: Operation In Scan Mode
Chapter 14 A/D Converter 14.6.2 Operation in scan mode The pins from the conversion start analog input pin through the conversion termination analog input pin, specified in the ADSCM0 register, are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCRm register corresponding to the analog input (m = 0 to 11). When conver- sion stops through the last analog input pin, an A/D conversion interrupt (INTAD) is generated, which terminates A/D conversion (CS bit of ADSCM0 register = 0).
Page 508: Operation In A/D Trigger Polling Mode
Chapter 14 A/D Converter 14.7 Operation in A/D Trigger Polling Mode Setting the CE bit of the ADSCM0 register to 1 starts the A/D conversion immediately. Both select mode and scan mode can be continued with A/D trigger polling mode. Since the CS bit of the ADSCM0 register remains 1 after an INTAD interrupt in this mode, it is not necessary to set the CE bit to restart the A/D conversion.
Page 509: Operation In Scan Mode
Chapter 14 A/D Converter 14.7.2 Operation in scan mode The pins from the first analog input pin through the last analog input pin, specified in the ADSCM0 reg- ister, are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCRm register corresponding to the analog input (m = 0 to 11).
Page 510: Operation In Timer Trigger Mode
Chapter 14 A/D Converter 14.8 Operation in Timer Trigger Mode The A/D converter can set an interrupt signal as a conversion trigger for up to 12 channels of analog input (ANI0 to ANI11). The interrupt signal that can be selected as trigger is the Timer E 0 interrupt INTPE10/TINTCCE10. 14.8.1 Operation in select mode One analog input (ANI0 to ANI) specified by the ADSCM0 register is A/D converted.
Page 511: Operation In Scan Mode
Chapter 14 A/D Converter 14.8.2 Operation in scan mode Analog input pins specified by register ADSCM0 are selected sequentially, and the specified number of A/D conversions are performed by using the Timer E 0 interrupt as a trigger. The conversion results are stored in the ADCRm registers corresponding to the analog inputs (m = 0 to 11).
Page 512: Figure 14-14: Example Of Timer Trigger Scan Mode Operation (Ani1 To Ani4)
Chapter 14 A/D Converter Figure 14-14: Example of Timer Trigger Scan Mode Operation (ANI1 to ANI4) ANI0 ADCR0 ANI1 ADCR1 INTPE10/TINTCCE10 ANI2 ADCR2 A/D converter ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI11 ADCR11 (1) CE bit of ADSCM0 = 1 (Enabled) (7) A/D conversion of ANI3 (2) INTPE10/TINTCCE10 interrupt generation (8) Store conversion result in ADCR3...
Page 513: Precautions
Chapter 14 A/D Converter 14.9 Precautions 14.9.1 Stopping conversion operation If the CE bit of the ADSCM0 register is cleared during conversion operation, all conversion operations are stopped, and a conversion result is not stored in the ADCRm register (m = 0 to 11). 14.9.2 Trigger input during conversion operation If a trigger is input during conversion operation, that trigger input is ignored.
Page 514 Chapter 14 A/D Converter [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 515: Chapter 15 Port Functions
Chapter 15 Port Functions 15.1 Features • Input/Output ports: 89 • Ports alternate as input/output pins of other peripheral functions • Input or output can be specified in bit units Preliminary User’s Manual U14879EE1V0UM00...
Page 516: Port Configuration
Chapter 15 Port Functions 15.2 Port Configuration The V850E/VANStorm incorporates a total of 89 input/output ports, named ports P1 through P6, and PAL, PAH, PDL, PCS, PCT and PCM. The configuration is shown below. Figure 15-1: Port Configuration PAL0 Port 1...
Page 517 Chapter 15 Port Functions Functions of each port The V850E/VANStorm has the ports shown below. Any port can operate in 8- or 1-bit units and can provide a variety of controls. Moreover, besides its function as a port, each has functions as the input/output pins of on-chip peripheral I/O in control mode.
Page 518 Chapter 15 Port Functions Functions of each port pin on reset and registers that set port or control mode Port Name Pin Name Pin Function after Reset Mode-Setting Register Single-Chip Mode Port 1 P10/CRXD1 P10 (Input mode) PMC1 P11/CTXD1 P11 (Input mode) P12 (Input mode) P13 (Input mode) P14 (Input mode)
Page 519 Chapter 15 Port Functions Port Name Pin Name Pin Function after Reset Mode-Setting Register Single-Chip Mode Port 6 P60/CCLK P60 (Input mode) PMC6 P61/INT0 P61 (Input mode) P62/INT1 P62 (Input mode) P63/INT2 P63 (Input mode) P64/RXD2 P64 (Input mode) P65/TXD2 P65 (Input mode) Port CM PCM0/WAIT...
Page 520: Figure 15-2: Type A Block Diagram
Chapter 15 Port Functions Port block diagrams Figure 15-2: Type A Block Diagram WR PMCNn PMCNn WR PMNn PMNn Peripheral WR PNn Function Address RD PNn Peripheral Function Remark: N=1..6: Port number Port bit Preliminary User’s Manual U14879EE1V0UM00...
Page 521: Figure 15-3: Type B Block Diagram
Chapter 15 Port Functions Figure 15-3: Type B Block Diagram WR PMCALn PMCALn WR PMALn PMALn A15-A0 PALn WRPALn PALn Address RD PALn Remark: n=15 to 0 Preliminary User’s Manual U14879EE1V0UM00...
Page 522: Figure 15-4: Type C Block Diagram
Chapter 15 Port Functions Figure 15-4: Type C Block Diagram WR PMCAHn PMCAHn WR PMAHn PMAHn A23-A16 PAHn WRPAHn PAHn Address RD PAHn Remark: n=7 to 0 Preliminary User’s Manual U14879EE1V0UM00...
Page 523: Figure 15-5: Type D Block Diagram
Chapter 15 Port Functions Figure 15-5: Type D Block Diagram WR PMCDLn ROM-less = 1 Other = 0 PMCDLn WR PMDLn PMDLn DC0, DC1 from MEMC D15-D0 WR PDLn PDLn PDLn MEMC: DC0, DC1 Address RD PDLn Remark: n=15 to 0 Preliminary User’s Manual U14879EE1V0UM00...
Page 524: Figure 15-6: Type E Block Diagram
Chapter 15 Port Functions Figure 15-6: Type E Block Diagram WR PMCCSn PMCCSn WR PMCSn PMCSn PCSn CS2, CS3, CS4 WRPCSn PCSn Address RD PCSn Remark: n= 2, 3, 4 Preliminary User’s Manual U14879EE1V0UM00...
Page 525: Figure 15-7: Type F Block Diagram
Chapter 15 Port Functions Figure 15-7: Type F Block Diagram WR PMCCTn PMCCTn WR PMCTn PMCTn WR0, WR1, RD PCTn WR PCTn PCTn Address RD PCTn Remark: n= 5 to 0 Preliminary User’s Manual U14879EE1V0UM00...
Page 526: Figure 15-8: Type G Block Diagram
Chapter 15 Port Functions Figure 15-8: Type G Block Diagram WR PMCCM0 PMCCM0 WR PMCM0 PMCM0 WR PCM0 PCM0 PCM0 Address RD PCM0 WAIT Preliminary User’s Manual U14879EE1V0UM00...
Page 527: Figure 15-9: Type H Block Diagram
Chapter 15 Port Functions Figure 15-9: Type H Block Diagram WR PMCCM1 PMCCM1 WR PMCM1 PMCM1 CLKOUT PCM1 WR PCM1 PCM1 Address RD PCM1 Preliminary User’s Manual U14879EE1V0UM00...
Page 528: Pin Functions Of Each Port
Chapter 15 Port Functions 15.3 Pin Functions of Each Port 15.3.1 Port 1 Port 1 is a 7-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-10: Port 1 (P1) Address At Reset FFFFF400H Bit position Bit name Function...
Page 529: Figure 15-12: Port 1 Mode Control Register (Pmc1)
Chapter 15 Port Functions (b) Port 1 mode control register (PMC1) This register can be read or written in 8- or 1-bit units. Figure 15-12: Port 1 Mode Control Register (PMC1) Address At Reset PMC1 PMC11 PMC10 FFFFF44CH Bit Position Bit Name Function PMC11...
Page 530: Port 2
Chapter 15 Port Functions 15.3.2 Port 2 Port 2 is a 8-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-13: Port 2 (P2) Address At Reset FFFFF402H Bit position Bit name Function 7 to 0 Input/output port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (CSI0, CSI1,...
Page 531: Figure 15-15: Port 2 Mode Control Register (Pmc2)
Chapter 15 Port Functions (b) Port 2 mode control register (PMC2) This register can be read or written in 8- or 1-bit units. Figure 15-15: Port 2 Mode Control Register (PMC2) Address At Reset PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 FFFFF442H Bit Position Bit Name...
Page 532: Port 3
Chapter 15 Port Functions 15.3.3 Port 3 Port 3 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-16: Port 3 (P3) Address At Reset FFFFF404H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 533: Figure 15-18: Port 3 Mode Control Register (Pmc3)
Chapter 15 Port Functions (b) Port 3 mode control register (PMC3) This register can be read or written in 8- or 1-bit units. Figure 15-18: Port 3 Mode Control Register (PMC3) Address At Reset PMC3 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF444H Bit Position Bit Name...
Page 534: Port 4
Chapter 15 Port Functions 15.3.4 Port 4 Port 4 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-19: Port 4 (P4) Address At Reset FFFFF406H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 535: Figure 15-21: Port 4 Mode Control Register (Pmc4)
Chapter 15 Port Functions (b) Port 4 mode control register (PMC4) This register can be read or written in 8- or 1-bit units. Figure 15-21: Port 4 Mode Control Register (PMC4) Address At Reset PMC4 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF446H Bit Position Bit Name...
Page 536: Port 5
Chapter 15 Port Functions 15.3.5 Port 5 Port 5 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-22: Port 5 (P5) Address At Reset FFFFF408H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 537: Figure 15-24: Port 5 Mode Control Register (Pmc5)
Chapter 15 Port Functions (b) Port 5 mode control register (PMC5) This register can be read or written in 8- or 1-bit units. Figure 15-24: Port 5 Mode Control Register (PMC5) Address At Reset PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 FFFFF448H Bit Position Bit Name...
Page 538: Port 6
Chapter 15 Port Functions 15.3.6 Port 6 Port 6 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-25: Port 6 (P6) Address At Reset FFFFF40AH Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as external CAN clock supply, serial...
Page 539: Figure 15-27: Port 6 Mode Control Register (Pmc6)
Chapter 15 Port Functions (b) Port 6 mode control register (PMC6) This register can be read or written in 8- or 1-bit units. Figure 15-27: Port 6 Mode Control Register (PMC6) Address At Reset PMC6 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 FFFFF44AH Bit Position Bit Name...
Page 540: Port Al
Chapter 15 Port Functions 15.4 Port AL Port AL is a 16-/8-bit input/output port that can be set the input or output mode in 1-bit units. Figure 15-28: Port AL (PAL) Address Reset PAL PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 FFFFF000H 0000H Bit position Bit name Function...
Page 541: Figure 15-30: Port Al Mode Control Register (Pmcal)
Chapter 15 Port Functions (b) Port AL mode control register (PMCAL) This register can be read/written in 16-, 8-, or 1-bit units. Figure 15-30: Port AL Mode Control Register (PMCAL) Address Reset PMCAL PMCAL15 PMCAL14 PMCAL13 PMCAL12 PMCAL11 PMCAL10 PMCAL9 PMCAL8 PMCAL7 PMCAL6 PMCAL5 PMCAL4 PMCAL3 PMCAL2 PMCAL1 PMCAL0 FFFFF040H 0000H Bit Position Bit Name Function...
Page 542: Port Ah
Chapter 15 Port Functions 15.5 Port AH Port AH is a 16-bit input/output port for which input/output can be specified bitwise. Figure 15-31: Port AH (PAH) Address Reset PAH8 PAH7 PAH6 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0 FFFFF002H 00H Bit position Bit name Function 8 to 0...
Page 543: Figure 15-33: Port Ah Mode Control Register (Pmcah)
Chapter 15 Port Functions (b) Port Mode Control Register AH (PMCAH) PMCAH can be read/written from/to in 16-bit units or bitwise. Figure 15-33: Port AH Mode Control Register (PMCAH) Address Reset PMCAH PMCAH7 PMCAH6 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 FFFFF042H 00H Bit Position Bit Name Function...
Page 544: Port Dl
Chapter 15 Port Functions 15.6 Port DL Port DL is a 16-bit input/output port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit input/output port that can specify input/output in 1-bit units.
Page 545: Figure 15-36: Port Dl Mode Control Register (Pmcdl)
Chapter 15 Port Functions (b) Port DL mode control register (PMCDL) The PMCDL register can be read or written in 16-bit units. When using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, it can be read or written in 8- or 1-bit units.
Page 546: Port Cs
Chapter 15 Port Functions 15.7 Port CS Port CS is a 3-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-37: Port CS (PCS) Address At Reset PCS4 PCS3 PCS2 FFFFF008H Bit Position Bit Name Function 7 to 0 PCSn...
Page 547: Figure 15-39: Port Cs Mode Control Register (Pmccs)
Chapter 15 Port Functions (b) Port CS mode control register (PMCCS) This register can be read or written in 8- or 1-bit units. Figure 15-39: Port CS Mode Control Register (PMCCS) Address At Reset PMCCS PMCCS4 PMCCS3 PMCCS2 FFFFF048H Bit Position Bit Name Function 7 to 0...
Page 548: Port Ct
Chapter 15 Port Functions 15.8 Port CT Port CT is an 8-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-40: Port CT (PCT) Address At Reset PCT4 PCT3 PCT2 PCT1 PCT0 FFFFF00AH Bit Position Bit Name Function 7 to 0...
Page 549: Figure 15-42: Port Ct Mode Control Register (Pmcct)
Chapter 15 Port Functions (b) Port CT mode control register (PMCCT) This register can be read or written in 8- or 1-bit units. Figure 15-42: Port CT Mode Control Register (PMCCT) Address At Reset PMCCT PMCCT4 PMCCT3 PMCCT2 PMCCT1 PMCCT0 FFFFF04AH Bit Position Bit Name...
Page 550: Port Cm
Chapter 15 Port Functions 15.9 Port CM Port CM is a 2-bit input/output port in which input or output can be specified in 1-bit units. Figure 15-43: Port CM (PCM) Address At Reset PCM1 PCM0 FFFFF00CH Bit Position Bit Name Function 1, 0 PCM1, PCM0 Input/output port...
Page 551: Figure 15-45: Port Cm Mode Control Register (Pmccm)
Chapter 15 Port Functions (b) Port CM mode control register (PMCCM) This register can be read or written in 8- or 1-bit units. Figure 15-45: Port CM Mode Control Register (PMCCM) Address At Reset PMCCM PMCCM1 PMCCM0 FFFFF04CH Bit Position Bit Name Function PMCCM1...
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Page 553: Chapter 16 Reset Function
Chapter 16 RESET Function When a low level is input to the RESET pin, there is a system reset and each hardware item of the V850E/ VANStorm is initialized to its initial status. When the RESET pin changes from low level to high level, reset status is released and the CPU starts program execution.
Page 554: Figure 16-1: Reset Signal Acknowledgment
Chapter 16 RESET Function Reset signal acknowledgment Figure 16-1: Reset signal acknowledgment RESET Analog Analog Analog delay delay delay Elimination as noise Internal system Note reset signal Reset acknowledgment Reset release Note: The internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET signal.
Page 555: Initialization
Chapter 16 RESET Function 16.3 Initialization Initialize the contents of each register as needed within a program. Table 16-2 shows the initial values of the CPU and internal RAM after reset. The initial values of on-chip peripheral I/O’s after reset can be found in Table 16-2. Table 16-2: Initial Values of CPU and Internal RAM After Reset On-Chip Hardware Register Name...
Page 556 Chapter 16 RESET Function [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 557: Chapter 17 Voltage Regulator
Chapter 17 Voltage Regulator 17.1 Outline The V850E/VANStorm incorporates two regulators to realize a 5-V single power supply, low power con- sumption, and to reduce noise. These regulators supply a voltage obtained by stepping down V power supply voltage to oscillation blocks and on chip logic circuits (excluding the A/D converter and output buffers).
Page 558 [MEMO] Preliminary User’s Manual U14879EE1V0UM00...
Page 559: Chapter 18 Internal Voltage Comparator
Chapter 18 Internal Voltage Comparator 18.1 Features • Input voltage comparison by comparator • The comparator compares an internal reference voltage with an input voltage at the comparator input pin VCMPIN. The comparison result can be read in the interrupt status flag. •...
Page 560: Voltage Comparator Functions
Chapter 18 Internal Voltage Comparator 18.2 Voltage Comparator Functions The V850E/ VANStorm device is designed to operate in a wide range of power supply from 3.5 V to 5.5 V. The conditions with respect to the operating voltages V conforms to the following specification: Table 18-1: Power Supply Voltage Operating Modes Supply Voltage Range...
Page 561: Figure 18-2: Internal Voltage Comparator
Chapter 18 Internal Voltage Comparator The comparator threshold and hysteresis are set by three external resistors: Figure 18-2: Internal Voltage Comparator hysteresis VCMPOUT measure point VCMPIN Status-Register Flag- Ref. The threshold has to be set to a voltage above 4.5 V to guarantee the frequency change within the time the supply voltage drops below 4.5 V.
Page 562: Internal Voltage Comparator Control Register (Vcmpm)
Chapter 18 Internal Voltage Comparator 18.2.1 Internal voltage comparator control register (VCMPM) The VCMPN0 register is an 8-bit register, which defines the operation mode of the internal voltage com- parator. This register can be read/ written in 8- or 1-bit units. Address At Reset VCMPM...
Page 563: Chapter 19 Flash Memory
Chapter 19 Flash Memory The V850E/ VANStorm provides a 256 KB flash memory. An instruction fetch from the flash memory takes one clock. The flash memory can be programmed using a dedicated flash writer. Furthermore this product has a Selfprogramming mode, which allows to program the flash memory by control of the application without any dedicated writer.
Page 564: Writing By Flash Writer
Chapter 19 Flash Memory 19.2 Writing by Flash writer Writing can be performed either on-board or off-board by the dedicated flash writer. On-board programming The contents of the flash memory is rewritten after the µPD76F0018 is mounted on the target sys- tem.
Page 565: Communication System
Chapter 19 Flash Memory 19.4 Communication System The communication between the dedicated flash writer and the µPD76F0018 is performed by serial communication using CSI. Transfer rate: up to 1.0 Mbps (MSB first) Figure 19-2: Flash Writer Communication via CSI0 DD5n SS5n SS3m RESET...
Page 566: Flash Programming Circuitry
Chapter 19 Flash Memory 19.5 Flash Programming Circuitry The following schematic shows the minimal circuitry. The circuitry incorporates a low-dropout voltage regulator (µPC29S78) as well as flash writer support. If the device is not used for Selfprogramming the pins have to be connected via a pull down resistor to ground and the voltage regulator (µPC29S78) can be removed.
Page 567: Pin Handling
Chapter 19 Flash Memory 19.6 Pin Handling When performing on-board writing, all required signals on the target system have to be made accessi- ble to the dedicated flash writer. Also, it has to be ensured that the modes are set correctly and the signal, which is required to enter the programming mode can be controlled by the flash writer.
Page 568: Serial Interface Pins
Chapter 19 Flash Memory 19.6.2 Serial interface pins The following shows the pins used by the serial interface. Serial Interface Pins Used CSI0 SO0,SI0,SCK0 When connecting a dedicated flash writer to a serial interface pin, which is connected to other devices on-board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc.
Page 569: Figure 19-6: Malfunction Of Other Input Pins
Chapter 19 Flash Memory Malfunction of the other device When connecting a flash writer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored.
Page 570: Reset Pin
Chapter 19 Flash Memory 19.6.3 RESET pin When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset signal generation circuit on-board, conflict of signals may happen. To avoid the conflict of sig- nals, isolate the connection to the reset signal generation circuit.
Page 571: Programming Method
Chapter 19 Flash Memory 19.7 Programming Method 19.7.1 Flash memory control To manipulate the flash memory the VANStorm has to operate in a special flash memory programming mode. This mode can be entered either by applying the programming voltage of 7.8 V to the V before the reset is release or by entering the Selfprogramming mode.
Page 572: Selfprogramming Mode
Chapter 19 Flash Memory 19.8 Selfprogramming Mode The flash Selfprogramming feature allows user to reprogram the flash contents by a user application program, without the necessity of an external flash writer. This feature allows an update of the application with only on-board resources and a user defined com- munication interface.
Page 573: Secure Selfprogramming
Chapter 19 Flash Memory 19.9 Secure Selfprogramming 19.9.1 General description A flash memory area can only be erased as a whole. If parts of the lower flash area have to be updated, the complete flash memory has to be erased. This bears the risk that a problem during Selfprogram- ming, particularly a power failure, leaves the device without any valid program for start-up.
Page 574: Figure 19-10: Secure Selfprogramming Flow (1/2)
Chapter 19 Flash Memory Figure 19-10: Secure Selfprogramming Flow (1/2) Area 1 Area 1 Area 1 0003FFFFH Bootprogram Upper Application Part 2 Erased Area Bootblock Size Signature Vector Table 00020000H Application Part 1 Application Part 1 Application Part 1 Bootprogram Bootprogram Bootprogram Lower...
Page 575: Advantages Of Secure Selfprogramming
Chapter 19 Flash Memory Figure 19-10: Secure Selfprogramming Flow (2/2) Area 0 Area 0 Area 0 0003FFFFH Application Part 1 Bootprogram New Application Upper Erased Part 2 Area Bootblock Size Vector Table 00020000H New Application Erased Erased Part 1 Bootprogram Bootprogram Bootprogram Lower...
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Page 577: Appendix A Instruction Set List
Appendix A Instruction Set List A.1 Convention (a) Register symbols used to describe operands Register Symbol Explanation reg1 General registers: Used as source registers reg2 General registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General registers: Used mainly to store the remainders of division results and the higher order 3 bits of multiplication results.
Page 578 Appendix A Instruction Set List (c) Register symbols used in operation Register Symbol Explanation ¨ Input for GR [ ] General register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 579 Appendix A Instruction Set List (e) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (f) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 580: Instruction Set (In Alphabetical Order)
Appendix A Instruction Set List A.2 Instruction Set (In Alphabetical Order) (1/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1] × × × × imm5,reg2 rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5) ×...
Page 581 Appendix A Instruction Set List (2/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT HALT Stop 0000011111100000 0000000100100000 × × × reg2,reg3 GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16) rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 GR[reg2]←PC + 4 rrrrr11110dddddd PC←PC + sign-extend(disp22) ddddddddddddddd0...
Page 582 Appendix A Instruction Set List (3/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT PREPARE list12,imm5 Store-memory(sp – 4,GR[reg in list12],Word) 0000011110iiiiiL sp←sp – 4 Note Note Note LLLLLLLLLLL00001 repeat 1 step above until all regs in list12 are stored sp←sp –...
Page 583 Appendix A Instruction Set List (4/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT ST.W reg2,disp16[reg1] rrrrr111011RRRRR adr←GR[reg1] + sign-extend(disp16) Store-memory (adr,GR[reg2], Word) ddddddddddddddd1 Note 8 STSR regID,reg2 GR[reg2]←SR[regID] rrrrr111111RRRRR 0000000001000000 × × × × reg1,reg2 rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1] ×...
Page 584 Appendix A Instruction Set List 16. ff = 00: Load sp in ep. 10: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18.
Page 585: Appendix B Index
Appendix B Index A/D conversion result registers 0 to 11 ..........499 A/D converter operation A/D trigger mode .
Page 586 Appendix B Index Clock select registers 0 to 2 ............313 Clocked serial interface clock selection registes 0, 1 .
Page 587 Appendix B Index Storage prority ............. . . 366 Time stamp .
Page 588 Appendix B Index P4 ................534 P40 to P45 .
Page 589 Appendix B Index A/D converter ..............513 Timer D .
Page 590 Appendix B Index Timer E software event capture registers 0 to 2 ........262 Timer E sub-channel 0 capture/compare registers 0 to 2 .
Page 591 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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