NEC UPD703116 User Manual page 222

(1) Timers 00, 01 (TM00, TM01)
TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3
(CM0n3) (n = 0, 1).
TM0n start/stop is controlled by the TM0CEn bit of timer control register 0n (TMC0n).
Division by the prescaler can be selected for the count clock from among f
f /32 with the PRM02 to PRM00 bits of the TMC0n register (f
CLK
selection register (PRM01)).
The conditions when TM0n becomes 0000H are as follows.
• Reset input
• TM0CEn bit = 0
• TM0n register and compare register 0n3 (CM0n3) match (PWM mode 2 (sawtooth wave) only)
• Immediately after overflow or underflow
The TM0n timer has 3 operation modes, shown in Table 9-1. The operation mode is selected with timer
control register 0n (TMC0n).
Operation Mode Count Operation
PWM mode 0 Up/down
(symmetric
triangular wave)
PWM mode 1 Up/down
(asymmetric
triangular wave)
PWM mode 2 Up
(sawtooth wave)
Caution An interrupt does not occur and the operation of timer 0 is not affected even if TM0ICn,
CM03ICn, or the interrupt mask flag of the IMR0 register (TM0MKn or CM03MKn) is set
(interrupts disabled) as the interrupt source.
Remark n = 0, 1
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CHAPTER 9 TIMER/COUNTER FUNCTION
Table 9-1. Timer 0 Operation Modes
Timer Clear Interrupt Source
Source
−
INTTM0n
INTCM0n3
−
INTTM0n
INTCM0n3
INTCM0n3 INTCM0n3
User's Manual U14492EJ5V0UD
, f /2, f
CLK CLK CLK
: base clock, see 9.1.4 (1) Timer 0 clock
CLK
BFCMn3 → CM0n3
BFCMn0 to BFCMn2→
Transfer Timing CM0n0 to CM0n2
INTTM0n
INTTM0n
INTCM0n3
/4, f /8, f /16,
CLK CLK
Transfer Timing
INTTM0n
INTTM0n
INTCM0n3
INTCM0n3