NEC UPD703116 User Manual page 498

(c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1)
INTCSIn is set (1) upon completion of data transmission/reception.
Caution The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the
CSICn register are not 111B). The delay mode cannot be set when the slave mode is set
(bits CKS2 to CKS0 = 111B).
Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2)
Input clock
SCKn (I/O)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn
interrupt
CSOTn bit
Remarks 1. n = 0, 1
2. Reg_R/W:
498
CHAPTER 10 SERIAL INTERFACE FUNCTION
(a) When CKP bit = 0, DAP bit = 0
DI7 DI6 DI5
DO7 DO6 DO5
Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed.
User's Manual U14492EJ5V0UD
DI4 DI3 DI2
DO4 DO3 DO2
DI1 DI0
DO1 DO0
Delay