NEC UPD703116 User Manual page 371

(2) Operation when TO2n pin output is controlled by manipulating OCTLE0.SWFEn bit in toggle mode 1
(a) When a sub-channel n compare match signal is output immediately after the SWFEn bit is cleared
to 0
Figures 9-86 and 9-87 show the waveforms when output from the TO2n output pin is started or ended by
manipulating the SWFEn bit in toggle mode 1.
In the V850E/IA1, timer 2 outputs a level according to the ALVEn bit setting (low level when ALVEn bit =
0, and high level when ALVEn bit = 1) by fixing the TO2n output to the inactive state when the SWFEn bit
is 1. When the SWFEn bit is 0, TO2n (internal) synchronizes with a trigger signal and an active or
inactive level is output from the TO2n output pin.
However, TO2n output is forcibly fixed to the active state when the SWFEn bit is cleared to 0, and
inactive state when the SWFEn bit is set to 1.
Therefore, if the sub-channel n compare match signal is output immediately after the SWFEn bit is
cleared to 0, the active period from when the SWFEn bit is cleared to 0 to when the compare match
signal is output will be added to the ordinary TO2n output active period, so the first active period
becomes long (refer to Figure 9-86).
Figure 9-86. When Output Operation Is Started/Ended Normally
(When OCTLE0 Register's OTMEn1, OTMEn0 Bits = 01, ODELD0 Register's ODLEn2 to ODLEn0 Bits = 000)
f
CLK
TM20 05 06 07
register
CVSE00
register
CVSEn0
TM20 = 0
register
CVSEn0
match signal
bit
SWFEn
Inactive state (fixed)
(internal)
TO2n
output
TO2n
(ALVEn bit = 0)
output
TO2n
(ALVEn bit = 1)
Remark n = 1 to 4
CHAPTER 9 TIMER/COUNTER FUNCTION
00 01 02 03 04 05 06
0008H
0005H
Active state
User's Manual U14492EJ5V0UD
07 00 01 02 03 04 05
Inactive state Active state Inactive state
06 07 00 01 02 03 04
Inactive state
(fixed)
05
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