NEC UPD703116 User Manual page 540

(3) Data bit synchronization
• Since the receiving node has no synchronization signal, synchronization is performed using level changes
that occur on the bus.
• As for the transmitting node, data is transmitted in sync with the transmitting node's bit timing.
(a) Hardware synchronization
This is bit synchronization that is performed when the receiving node has detected a start of frame in bus
idle mode.
• When a falling edge is detected on the bus, the current bit is assigned to the sync segment and the
next bit is assigned to the prop segment. In such cases, synchronization is performed regardless of
the SJW.
• Since bit synchronization must be established after a reset or after a wake-up, hardware
synchronization is performed only at the first level change that occurs on the bus (for the second and
subsequent level changes, bit synchronization is performed as shown below).
CAN bus
Bit timing
540
CHAPTER 11 FCAN CONTROLLER
Figure 11-22. Coordination of Data Bit Synchronization
Bus idle
Sync Prop
segment segment
User's Manual U14492EJ5V0UD
Start of frame
Phase Phase
segment 1 segment 2