Table of Contents
Advertisement
(7) Timer 2 sub-channel 0, 5 capture/compare control register (CMSE050)
The CMSE050 register controls timer 2 sub-channel 0 capture/compare register (CVSE00) and timer 2 sub-
channel 5 capture/compare register (CVSE50).
This register can be read/written in 16-bit units.
15
14
13
12
CMSE050
0
0
EEVE5
0
Bit position
Bit name
13, 5
EEVEn
11, 3
LNKEn
10, 2
CCSEn
Remark
m = 0, 1
n = 0, 5
CHAPTER 9 TIMER/COUNTER FUNCTION
11
10
9
8
7
6
LNKE5
CCSE5
0
0
0
0
Enables/disables event detection by sub-channel n capture/compare register.
0: ED1 and ED2 signal inputs ignored (nothing is done even if these signals are
input).
1: Operation caused by ED1 and ED2 signal inputs enabled.
Specifies capture event signal input from edge selection to ED1 or ED2.
0: In capture register mode, select ED1 signal input.
In compare register mode, LNKEn bit has no influence.
1: In capture register mode, select ED2 signal input.
In compare register mode, LNKEn bit has no influence.
Selects capture/compare register operation mode.
0: Operate in capture register mode. The TM20 and TM21 count statuses can be
read with sub-channel 0 and sub-channel 5, respectively.
1: Operate in compare register mode. TM2m is cleared upon detection of match
between sub-channel n and TM2m.
User's Manual U14492EJ5V0UD
5
4
3
2
1
0
EEVE0
0
LNKE0
CCSE0
0
0
Function
Address
Initial value
FFFFF64AH
0000H
343
Advertisement
Table of Contents
