NEC UPD703116 User Manual page 823

Edition
3rd Addition of Caution to 7.3.4 Interrupt control register (xxICn)
edition
Addition of Caution to 7.3.6 In-service priority register (ISPR)
Modification of description in Remark in 9.1.5 (2) PWM mode 0: Triangular wave
modulation (right-left symmetric waveform control)
Addition of Caution to 14.2 (1) Functions of each port
Modification of description in Figure 14-14 Example of Noise Elimination Timing
Addition of CHAPTER 18 ELECTRICAL SPECIFICATIONS
Addition of CHAPTER 19 PACKAGE DRAWING
Addition of CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN
Addition of APPENDIX E REVISION HISTORY
4th Addition of Note to Table 1-1 Differences Between V850E/IA1 and V850E/IA2
edition
Addition of Notes 1 and 2 to Table 1-2 Differences Between V850E/IA1 and V850E/IA2
Register Setting Values
Addition of Note to 1.4 Ordering Information
Addition of Note 3 to 1.5 Pin Configuration (Top View)
Addition of Caution to 3.4.5 (3) On-chip peripheral I/O area
Addition of Caution to 3.4.9 Programmable peripheral I/O registers and modification of
bit units for manipulation and initial values
Modification of description in 3.4.11 System wait control register (VSWC)
Addition of Note to 4.4 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
APPENDIX D REVISION HISTORY
Major Revision from Previous Edition
User's Manual U14492EJ5V0UD
(10/13)
Applied to:
CHAPTER 7
INTERRUPT/
EXCEPTION
PROCESSING
FUNCTION
CHAPTER 9
TIMER/COUNTER
FUNCTION (REAL-
TIME PULSE UNIT)
CHAPTER 14
PORT FUNCTIONS
CHAPTER 18
ELECTRICAL
SPECIFICATIONS
CHAPTER 19
PACKAGE
DRAWING
CHAPTER 20
RECOMMENDED
SOLDERING
CONDITIONS
APPENDIX A
NOTES ON
TARGET SYSTEM
DESIGN
APPENDIX E
REVISION
HISTORY
CHAPTER 1
INTRODUCTION
CHAPTER 3 CPU
FUNCTION
CHAPTER 4 BUS
CONTROL
FUNCTION
823