NEC UPD703116 User Manual page 300

(2) Timer unit mode registers 0, 1 (TUM0, TUM1)
The TUMn register is an 8-bit register used to specify the TM1n operation mode or to control the operation of
the PWM output pin.
TUMn can be read/written in 8-bit or 1-bit units.
Cautions 1. Changing the value of the TUMn register during TM1n operation (TM1CEn bit of TMCn
register = 1) is prohibited.
2. When the CMD bit = 0 (general-purpose timer mode), setting MSEL bit = 1 (UDC mode B)
is prohibited.
7 6
TUM0 CMD 0
7 6
TUM1 CMD 0
Bit position Bit name
7 CMD
3 TOE10
2 ALVT10
0 MSEL
Remark n = 0, 1
300
CHAPTER 9 TIMER/COUNTER FUNCTION
5 4 3
0 0 TOE10 ALVT10
5 4 3
0 0 TOE10 ALVT10
Specifies TM1n operation mode.
0: General-purpose timer mode (up count)
1: UDC mode (up/down count)
Specifies timer output (TO1n) enable.
0: Timer output disabled
1: Timer output enabled
Caution When CMD bit = 1 (UDC mode), timer output is not performed
regardless of the setting of the TOE10 bit. At this time, timer output
consists of the negative phase level of the level set by the ALVT10
bit.
Specifies active level of timer output (TO1n).
0: Active level is high level
1: Active level is low level
Caution When CMD bit = 1 (UDC mode), timer output is not performed
regardless of the setting of the TOE10 bit. At this time, timer output
consists of the negative phase level of the level set by the ALVT10
bit.
Specifies operation in UDC mode (up/down count).
0: UDC mode A
TM1n can be cleared by setting the CLR1, CLR0 bits of the TMC1n register.
1: UDC mode B
TM1n is cleared in the following cases.
• Upon match with CM1n0 during TM1n up-count operation
• Upon match with CM1n1 during TM1n down-count operation
When UDC mode B is set, the ENMD, CLR1, and CLR0 bits of the TMC1n
register becomes invalid.
User's Manual U14492EJ5V0UD
2 1 0
0 MSEL FFFFF5EBH
2 1 0
0 MSEL FFFFF60BH
Function
Address Initial value
00H
Address Initial value
00H