NEC UPD703116 User Manual page 376

(b) Selection of the internal count clock
TM3 operates as a free-running timer.
When an internal clock is specified as a count clock by timer control register 31 (TMC31), TM3 is counted
up for each input clock cycle specified by the CS2 to CS0 bits of the TMC30 register.
A division by the prescaler can be selected for the count clock from among f
f /32, f /64, f
CLK CLK
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following
an overflow by setting the OST bit of the TMC31 register to 1.
Caution The count clock cannot be changed while the timer is operating.
The conditions when the TM3 register becomes 0000H are shown below.
(i) Asynchronous reset
• TM3CAE bit of TMC30 register = 0
• Reset input
(ii) Synchronous reset
• TM3CE bit of TMC30 register = 0
• The CC30 register is used as a compare register, and the TM3 and CC30 registers match when
clearing the TM3 register is enabled (CCLR bit of the TMC31 register = 1)
376
CHAPTER 9 TIMER/COUNTER FUNCTION
/128 and f /256 by the TMC30 register (f
CLK CLK
User's Manual U14492EJ5V0UD
/2, f /4, f
CLK CLK
: base clock).
CLK
/8, f /16,
CLK CLK