NEC UPD703116 User Manual page 771

(1) Clock timing (1/2)
µ
= –40 to +85°C:
(T
A
µ
= –40 to +110°C:
T
A
V = CV = 3.0 to 3.6 V, V
DD3 DD
output pin load capacitance: C
Parameter
X1 input cycle
X1 input high-level width
X1 input low-level width
X1 input rise time
X1 input fall time
CPU operation frequency
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
CLKOUT fall time
Delay time from X1↓ to CLKOUT
Notes 1. –40°C ≤ T ≤ +110°C
A
2. –40°C ≤ T ≤ +85°C
A
3. When interfacing to the external devices using the CLKOUT signal, make the internal system clock
frequency (f ) 32 MHz or lower.
XX
Remark T = t
CYK
CHAPTER 18 ELECTRICAL SPECIFICATIONS
PD703116, 703116(A), 70F3116, 70F3116(A),
PD703116(A1), 70F3116(A1),
= 5 V ±0.5 V, V
DD5
= 50 pF)
L
Symbol
<1> t
CYX
<2> t
WXH
<3> t
WXL
<4> t
XR
<5> t
XF
−
f
XX
<6> t
CYK
<7> t
WKH
<8> t
WKL
<9> t
KR
<10> t
KF
<11> t
DXK
User's Manual U14492EJ5V0UD
= V = CV = 0 V,
SS3 SS5 SS
Conditions
Direct mode Note 1
PLL mode
Direct mode Note 2
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Note 2
Note 1
Note 3
CLKOUT signal used
Note 2
Note 1
Note 3
CLKOUT signal used
Direct mode
MIN. MAX. Unit
31.25 125 ns
156 250 ns
20 125 ns
156 250 ns
6 ns
50 ns
6 ns
50 ns
4 ns
10 ns
4 ns
10 ns
4 50 MHz
4 32 MHz
4 32 MHz
20 250 ns
31.25 250 ns
31.25 250 ns
0.5T – 9 ns
0.5T – 11 ns
11 ns
9 ns
40 ns
771