Debug Trap - NEC UPD703116 User Manual

7.5.2 Debug trap

The debug trap is an exception that can be acknowledged every time and is generated by execution of the
DBTRAP instruction.
When the debug trap is generated, the CPU performs the following processing.
(1) Operation
(1) Saves the restored PC to DBPC.
(2) Saves the current PSW to DBPSW.
(3) Sets the NP, EP and ID bits of the PSW.
(4) Sets the handler address (00000060H) corresponding to the debug trap to the PC and transfers control.
Figure 7-12 illustrates the processing of the debug trap.
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 7-12. Debug Trap Processing
CPU processing
Debug monitor routine processing
User's Manual U14492EJ5V0UD
DBTRAP instruction
DBPC restored PC
DBPSW PSW
PSW.NP 1
PSW.EP 1
PSW.ID 1
PC 00000060H
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