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(14) CAN global status register (CGST)
The CGST register indicates global status information.
This register can be read/written in 16-bit units.
Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to
write directly to this register may result in operation faults, so be sure to follow the
sequence described in 11.9 Cautions on Bit Set/Clear Function.
2. When writing to the CGST register, set or clear bits according to the register
configuration shown in part (b) Write.
15
14
13
12
CGST
0
0
0
0
(Read)
15
14
13
12
CGST
0
0
0
0
(Write)
(a) Read (1/2)
Bit position
Bit name
7
MERR
3
EFSD
Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable
peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being
set.
m = 2, 6, A, E
CHAPTER 11 FCAN CONTROLLER
11
10
9
8
7
6
0
0
0
1
MERR
0
7
11
10
9
8
6
clear
set
set
set
0
0
EFSD
TSM
GOM
MERR
This is the status flag that indicates an MAC error.
0: Error has not occurred after the MERR bit has been cleared.
1: Error occurred at least once after the MERR bit was cleared.
Caution MAC errors occur under the following conditions.
• When invalid address is accessed
• When access prohibited by MAC is performed
• When the GOM bit is cleared (0) before the INIT bit of the C1CTRL register
is set (1)
Indicates shutdown request.
0: Shutdown disabled
1: Shutdown enabled
Caution Be sure to set the EFSD bit (to 1) before clearing the GOM bit (to 0) (needs
to be accessed twice). The EFSD bit will be cleared (to 0) automatically
when the CGST register is accessed again.
User's Manual U14492EJ5V0UD
5
4
3
2
1
0
0
0
EFSD
TSM
0
GOM
5
4
3
2
1
0
clear
clear
clear
0
0
0
EFSD
TSM
GOM
Function
(1/3)
Address
Initial value
Note
xxxxmC10H
0100H
565
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