NEC UPD703116 User Manual page 178

(1) External interrupt mode registers 1, 2 (INTM1, INTM2)
These registers specify the valid edge for external interrupt requests (INTP0 to INTP6), input via external
pins. The correspondence between each register and the external interrupt requests that register controls is
shown below.
• INTM1: INTP0, INTP1, INTP2/ADTRG0, INTP3/ADTRG1
• INTM2: INTP4 to INTP6
INTP2 and INTP3 function alternately as ADTRG0 and ADTRG1 (A/D converter external trigger input).
Therefore, if the external trigger mode has been set by the TRG0 to TRG2 bits of A/D converter mode register
n0 (ADSCMn0), setting the ES20 and ES21, and ES30 and ES31 bits of INTM1 also specifies the valid edge
of the external trigger input (ADTRG0 and ADTRG1) (n = 0, 1).
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling
edges).
These registers can be read/written in 8-bit or 1-bit units.
7 6
INTM1 ES31 ES30
INTP3/ADTRG1
7 6
INTM2 0 0
Bit position Bit name
7 to 0 ESn1, ESn0
(INTM1), (n = 0 to 6)
5 to 0
(INTM2)
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5 4 3
ES21 ES20 ES11
INTP2/ADTRG0
5 4 3
ES61 ES60 ES51
INTP6
Specifies the valid edge of the INTPn, ADTRG0 and ADTRG1 pins.
ESn1 ESn0
0 0
0 1
1 0
1 1
User's Manual U14492EJ5V0UD
2 1 0
ES10 ES01 ES00
INTP1 INTP0
2 1 0
ES50 ES41 ES40
INTP5 INTP4
Function
Operation
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Address Initial value
FFFFF882H 00H
Address Initial value
FFFFF884H 00H