Table of Contents
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Edition
2nd
Addition of initial value 00H and modification of Caution in 16.7.12 Flash programming
edition
mode control register (FLPMC)
Addition of 16.7.13 Calling device internal processing
Addition of 16.7.14 Erasing flash memory flow
Addition of 16.7.15 Continuous writing flow
Addition of 16.7.16 Internal verify flow
Addition of 16.7.17 Acquiring flash information flow
Addition of 16.7.18 Self-programming library
Modification of Caution in 16.8 How to Distinguish Flash Memory and Mask ROM
Versions
Addition of CHAPTER 17 TURNING ON/OFF POWER
Modification of description in B.2 Instruction Set (Alphabetical Order)
3rd
Modification of description in 4.2.1 Pin status during internal ROM, internal RAM, and
edition
on-chip peripheral I/O access
Addition of description to 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
Addition of description to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to
DSA3H)
Addition of description to 6.3.2 DMA destination address registers 0 to 3 (DDA0 to
DDA3)
Addition of description to 6.3.2 (1) DMA destination address registers 0H to 3H
(DDA0H to DDA3H)
Addition of description to 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
Addition of description to 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to
DADC3)
Addition of description to 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to
DCHC3)
Addition and modification of description in 6.3.6 DMA disable status register (DDIS)
Addition of description to 6.3.7 DMA restart register (DRST)
Addition of description to 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
Modification of description in Table 6-1 Relationship Between Transfer Type and
Transfer Target
Modification of description in Remark in 6.7.1 Transfer type and transfer target
Modification and addition of description in 6.9 Next Address Setting Function
Modification of description in 6.11 Forcible Interruption
Modification of description in 6.14 (4) Bus arbitration for CPU
Addition of 6.14 (6) Execution of program and DMA transfer in internal RAM
822
APPENDIX D REVISION HISTORY
Major Revision from Previous Edition
User's Manual U14492EJ5V0UD
(9/13)
Applied to:
CHAPTER 16
FLASH MEMORY
µ
(
PD70F3116)
CHAPTER 17
TURNING ON/OFF
POWER
APPENDIX B
INSTRUCTION
SET LIST
CHAPTER 4 BUS
CONTROL
FUNCTION
CHAPTER 6 DMA
FUNCTIONS (DMA
CONTROLLER)
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