NEC UPD703116 User Manual page 457

(2) Transmission operation
The transmission operation is started by writing data to 2-frame continuous transmission shift registers 1, 2
(TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2).
Following data write, the start bit is transmitted from the next shift timing.
Since the UARTn does not have a CTS (transmission enable signal) input pin, use a port when the other
party confirms the reception enabled status (n = 1, 2).
(a) Transmission operation start
The transmission operation is started by writing transmit data to 2-frame continuous transmission shift
registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2). Then data is output in
sequence from LSB to the TXDn pin (transmission in sequence from the start bit). A start bit, parity bit,
and stop bit(s) are automatically added.
(b) Transmission interrupt request
When the transmit shift register becomes empty upon completion of the transmission of 1 or 2 frames of
data, a transmission completion interrupt request (INTSTn) is generated.
generation timing differs depending on the specified stop bit length. The INTSTn interrupt is generated at
the same time that the last stop bit is output.
The transmission operation remains stopped until the data to be transmitted next has been written to the
TXSn/TXSLn registers.
Figure 10-17 shows the INTSTn interrupt generation timing.
Cautions 1. Normally, the transmission completion interrupt (INTSTn) is generated when the
transmit shift register becomes empty.
become empty due to input of RESET, no transmission completion interrupt (INTSTn) is
generated.
2. No data can be written to the TXSn or TXSLn registers during transmission operation
until INTSTn is generated. Even if data is written, this does not affect the transmission
operation.
CHAPTER 10 SERIAL INTERFACE FUNCTION
User's Manual U14492EJ5V0UD
The INTSTn interrupt
However, if the transmit shift register has
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