NEC UPD703116 User Manual page 775

Remarks 1. T = t
CYK
2. w: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1)
4. w : Number of address setup wait states (0 or 1)
AS
5. w : Number of address hold wait states (0 or 1)
AH
6. Observe at least either of the data input hold time t
7. For the number of wait clocks to be inserted, refer to 4.6.3 Relationship between programmable
wait and external wait.
(b) CLKOUT synchronous (T
Parameter
Delay time from CLKOUT↑ to address
Delay time from CLKOUT↑ to address float
Delay time from CLKOUT↓ to ASTB
Delay time from CLKOUT↑ to RD, LWR, UWR
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Delay time from CLKOUT↑ to data output
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
Delay time from CLKOUT↑ to HLDAK
Delay time from CLKOUT↑ to address float
Remarks 1. T = t
CYK
2. w : Number of address hold wait states (0 or 1)
AH
3. Observe at least either of the data input hold time t
CHAPTER 18 ELECTRICAL SPECIFICATIONS
= –40 to +85°C: µ
PD703116, 703116(A), 70F3116, 70F3116(A),
A
= –40 to +110°C: µ
T PD703116(A1), 70F3116(A1),
A
V = CV = 3.0 to 3.6 V, V
DD3 DD
output pin load capacitance: C
Symbol
<45> t
DKA
<46> t
FKA
<47> t
DKST
<48> t
DKRDWR
<49> t
SIDK
<50> t
HKID
<51> t
DKOD
<52> t
SWTK
<53> t
HKWT
<54> t
SHQK
<55> t
HKHQ
<56> t
DKHA
<57> t
DKF
User's Manual U14492EJ5V0UD
t .
or
HKID HRDID
= 5 V ±0.5 V, V
= V
DD5 SS3
= 50 pF)
L
Conditions MIN.
–7
–12
–3 + w
–5
21
5
21
5
21
5
t .
or
HKID HRDID
= CV = 0 V,
SS5 SS
MAX. Unit
19 ns
15 ns
T 19 + w T ns
AH AH
19 ns
ns
ns
19 ns
ns
ns
ns
ns
19 ns
19 ns
775