NEC UPD703116 User Manual page 357

(3) Operation of capture/compare register (sub-channels 1 to 4)
Sub-channels 1 to 4 receive the count value of the timer 2 multiplex count generator.
The multiplex count generator is an internal unit of TM2n that supplies the multiplex count value MUXCNT to
sub-channels 1 to 4. The count value of TM20 is output to sub-channels 1 to 4 at the rising edge of MUXTB0,
and the count value of TM21 is output to sub-channels 1 to 4 at the rising edge of MUXTB1.
Figure 9-71 shows the block diagram of the timer 2 multiplex count generator, and Figure 9-72 shows the
multiplex count timing.
Figure 9-71. Block Diagram of Timer 2 Multiplex Count Generator
f
CLK
CNT (from TM20)
CNT (from TM21)
Remarks 1. f : Base clock
CLK
2. CNT: Count value of timer 2
MUXTB0, MUXTB1: Multiplex signal of TM20, TM21
MUXCNT: Count value to sub-channel m
3. m = 1 to 4
CHAPTER 9 TIMER/COUNTER FUNCTION
Multiplex control
Timer 2 multiplex
count generator
User's Manual U14492EJ5V0UD
MUXTB0
(to sub-channel m capture/compare register)
MUXTB1
(to sub-channel m capture/compare register)
MUXCNT
(to sub-channel m capture/compare register)
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